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<!@TC:1741115661>
#Build: Synplify Pro (R) U-2023.03L-SP1, Build 153R, Aug 10 2023
#install: C:\lscc\diamond\3.13\synpbase
#OS: Windows 10 or later
#Hostname: DESKTOP-L92NLN5

# Wed Mar  5 03:14:21 2025

#Implementation: impl1


Copyright (C) 1994-2023 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: U-2023.03L-SP1
Install: C:\lscc\diamond\3.13\synpbase
OS: Windows 10 or later
Hostname: DESKTOP-L92NLN5

Implementation : impl1
<a name=compilerReport1></a>Synopsys HDL Compiler, Version comp202303synp1, Build 155R, Built Aug 10 2023 09:42:17, @</a>

@N: : <!@TM:1741115669> | Running in 64-bit mode 
###########################################################[

Copyright (C) 1994-2023 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: U-2023.03L-SP1
Install: C:\lscc\diamond\3.13\synpbase
OS: Windows 10 or later
Hostname: DESKTOP-L92NLN5

Implementation : impl1
<a name=compilerReport2></a>Synopsys Verilog Compiler, Version comp202303synp1, Build 155R, Built Aug 10 2023 09:42:17, @</a>

@N: : <!@TM:1741115669> | Running in 64-bit mode 
@I::"C:\lscc\diamond\3.13\synpbase\lib\lucent\machxo2.v" (library work)
@I::"C:\lscc\diamond\3.13\synpbase\lib\lucent\pmi_def.v" (library work)
@I::"C:\lscc\diamond\3.13\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"C:\lscc\diamond\3.13\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"C:\lscc\diamond\3.13\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\bin_to_bcd.v" (library work)
@I::"D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\decoder.v" (library work)
@I::"D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\prox_detect.v" (library work)
@I::"D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\rpr0521rs_driver.v" (library work)
@I::"D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v" (library work)
Verilog syntax check successful!
Selecting top level module prox_detect
@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\rpr0521rs_driver.v:18:7:18:23:@N:CG364:@XP_MSG">rpr0521rs_driver.v(18)</a><!@TM:1741115669> | Synthesizing module rpr0521rs_driver in library work.
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\rpr0521rs_driver.v:154:56:154:59:@N:CG179:@XP_MSG">rpr0521rs_driver.v(154)</a><!@TM:1741115669> | Removing redundant assignment.
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\rpr0521rs_driver.v:157:56:157:59:@N:CG179:@XP_MSG">rpr0521rs_driver.v(157)</a><!@TM:1741115669> | Removing redundant assignment.
<font color=#A52A2A>@W:<a href="@W:CG1340:@XP_HELP">CG1340</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\rpr0521rs_driver.v:161:47:161:53:@W:CG1340:@XP_MSG">rpr0521rs_driver.v(161)</a><!@TM:1741115669> | Index into variable data_wr could be out of range ; a simulation mismatch is possible.</font>
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\rpr0521rs_driver.v:169:53:169:58:@N:CG179:@XP_MSG">rpr0521rs_driver.v(169)</a><!@TM:1741115669> | Removing redundant assignment.
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\rpr0521rs_driver.v:176:54:176:57:@N:CG179:@XP_MSG">rpr0521rs_driver.v(176)</a><!@TM:1741115669> | Removing redundant assignment.
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\rpr0521rs_driver.v:179:54:179:57:@N:CG179:@XP_MSG">rpr0521rs_driver.v(179)</a><!@TM:1741115669> | Removing redundant assignment.
Running optimization stage 1 on rpr0521rs_driver .......
<font color=#A52A2A>@W:<a href="@W:CL265:@XP_HELP">CL265</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@W:CL265:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115669> | Removing unused bit 7 of dev_addr[7:0]. Either assign all bits or reduce the width of the signal.</font>
@A:<a href="@A:CL282:@XP_HELP">CL282</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@A:CL282:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115669> | Feedback mux created for signal dev_addr[6:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@A:<a href="@A:CL282:@XP_HELP">CL282</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@A:CL282:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115669> | Feedback mux created for signal reg_data[7:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@A:<a href="@A:CL282:@XP_HELP">CL282</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@A:CL282:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115669> | Feedback mux created for signal reg_addr[7:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@A:<a href="@A:CL282:@XP_HELP">CL282</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@A:CL282:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115669> | Feedback mux created for signal prox_dat[15:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@A:<a href="@A:CL282:@XP_HELP">CL282</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@A:CL282:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115669> | Feedback mux created for signal data_wr[7:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@A:<a href="@A:CL282:@XP_HELP">CL282</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@A:CL282:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115669> | Feedback mux created for signal data_r[7:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@A:<a href="@A:CL282:@XP_HELP">CL282</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@A:CL282:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115669> | Feedback mux created for signal dat_valid. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@A:<a href="@A:CL282:@XP_HELP">CL282</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@A:CL282:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115669> | Feedback mux created for signal dat_l[7:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@A:<a href="@A:CL282:@XP_HELP">CL282</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@A:CL282:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115669> | Feedback mux created for signal dat_h[7:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@A:<a href="@A:CL282:@XP_HELP">CL282</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@A:CL282:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115669> | Feedback mux created for signal ch1_dat[15:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@A:<a href="@A:CL282:@XP_HELP">CL282</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@A:CL282:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115669> | Feedback mux created for signal ch0_dat[15:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@N:CL189:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115669> | Register bit reg_addr[4] is always 0.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@N:CL189:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115669> | Register bit reg_addr[5] is always 0.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@N:CL189:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115669> | Register bit reg_addr[6] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@N:CL189:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115669> | Register bit reg_addr[7] is always 0.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@N:CL189:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115669> | Register bit reg_data[4] is always 0.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@N:CL189:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115669> | Register bit reg_data[5] is always 0.
<font color=#A52A2A>@W:<a href="@W:CL190:@XP_HELP">CL190</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@W:CL190:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115669> | Optimizing register bit state_back[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:CL190:@XP_HELP">CL190</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@W:CL190:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115669> | Optimizing register bit state_back[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@N:CL189:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115669> | Register bit dev_addr[0] is always 0.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@N:CL189:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115669> | Register bit dev_addr[1] is always 0.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@N:CL189:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115669> | Register bit dev_addr[2] is always 0.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@N:CL189:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115669> | Register bit dev_addr[3] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@N:CL189:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115669> | Register bit dev_addr[4] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@N:CL189:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115669> | Register bit dev_addr[5] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@N:CL189:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115669> | Register bit dev_addr[6] is always 0.
<font color=#A52A2A>@W:<a href="@W:CL279:@XP_HELP">CL279</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@W:CL279:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115669> | Pruning register bits 7 to 4 of reg_addr[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.</font>
<font color=#A52A2A>@W:<a href="@W:CL279:@XP_HELP">CL279</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@W:CL279:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115669> | Pruning register bits 5 to 4 of reg_data[7:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.</font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@W:CL169:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115669> | Pruning unused register ack_cl. Make sure that there are no unused intermediate registers.</font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@W:CL169:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115669> | Pruning unused register ack_cl. Make sure that there are no unused intermediate registers.</font>
<font color=#A52A2A>@W:<a href="@W:CL279:@XP_HELP">CL279</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@W:CL279:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115669> | Pruning register bits 3 to 2 of state_back[3:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.</font>
Finished optimization stage 1 on rpr0521rs_driver (CPU Time 0h:00m:00s, Memory Used current: 94MB peak: 95MB)
@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\bin_to_bcd.v:18:7:18:17:@N:CG364:@XP_MSG">bin_to_bcd.v(18)</a><!@TM:1741115669> | Synthesizing module bin_to_bcd in library work.
<font color=#A52A2A>@W:<a href="@W:CG215:@XP_HELP">CG215</a> : <a href="C:\lscc\diamond\3.13\synpbase\lib\lucent\machxo2.v:@W:CG215:@XP_MSG">machxo2.v</a><!@TM:1741115669> | Unrecognized attribute .repeat_statement on loop statement</font>
Running optimization stage 1 on bin_to_bcd .......
Finished optimization stage 1 on bin_to_bcd (CPU Time 0h:00m:01s, Memory Used current: 138MB peak: 139MB)
@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\decoder.v:18:7:18:14:@N:CG364:@XP_MSG">decoder.v(18)</a><!@TM:1741115669> | Synthesizing module decoder in library work.
@N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\decoder.v:37:15:37:24:@N:CG179:@XP_MSG">decoder.v(37)</a><!@TM:1741115669> | Removing redundant assignment.
Running optimization stage 1 on decoder .......
<font color=#A52A2A>@W:<a href="@W:CL279:@XP_HELP">CL279</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\decoder.v:33:0:33:6:@W:CL279:@XP_MSG">decoder.v(33)</a><!@TM:1741115669> | Pruning register bits 15 to 12 of prox_dat2[15:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.</font>
<font color=#A52A2A>@W:<a href="@W:CL279:@XP_HELP">CL279</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\decoder.v:33:0:33:6:@W:CL279:@XP_MSG">decoder.v(33)</a><!@TM:1741115669> | Pruning register bits 8 to 0 of prox_dat2[15:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.</font>
Finished optimization stage 1 on decoder (CPU Time 0h:00m:00s, Memory Used current: 139MB peak: 140MB)
@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:18:7:18:19:@N:CG364:@XP_MSG">segment_scan.v(18)</a><!@TM:1741115669> | Synthesizing module segment_scan in library work.
Running optimization stage 1 on segment_scan .......
@A:<a href="@A:CL282:@XP_HELP">CL282</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:91:0:91:6:@A:CL282:@XP_MSG">segment_scan.v(91)</a><!@TM:1741115669> | Feedback mux created for signal data[15:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[0][0] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[0][1] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[0][2] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[0][3] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[0][4] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[0][5] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[0][6] is always 0.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[1][0] is always 0.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[1][1] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[1][2] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[1][3] is always 0.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[1][4] is always 0.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[1][5] is always 0.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[1][6] is always 0.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[2][0] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[2][1] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[2][2] is always 0.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[2][3] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[2][4] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[2][5] is always 0.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[2][6] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[3][0] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[3][1] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[3][2] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[3][3] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[3][4] is always 0.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[3][5] is always 0.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[3][6] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[4][0] is always 0.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[4][1] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[4][2] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[4][3] is always 0.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[4][4] is always 0.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[4][5] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[4][6] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[5][0] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[5][1] is always 0.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[5][2] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[5][3] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[5][4] is always 0.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[5][5] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[5][6] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[6][0] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[6][1] is always 0.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[6][2] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[6][3] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[6][4] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[6][5] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[6][6] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[7][0] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[7][1] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[7][2] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[7][3] is always 0.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[7][4] is always 0.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[7][5] is always 0.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[7][6] is always 0.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[8][0] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[8][1] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[8][2] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[8][3] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[8][4] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[8][5] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[8][6] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[9][0] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[9][1] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[9][2] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[9][3] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[9][4] is always 0.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[9][5] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[9][6] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[10][0] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[10][1] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[10][2] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[10][3] is always 0.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[10][4] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[10][5] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[10][6] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[11][0] is always 0.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[11][1] is always 0.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[11][2] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[11][3] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[11][4] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[11][5] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[11][6] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[12][0] is always 1.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[12][1] is always 0.
@N:<a href="@N:CL189:@XP_HELP">CL189</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:51:0:51:6:@N:CL189:@XP_MSG">segment_scan.v(51)</a><!@TM:1741115669> | Register bit seg[12][2] is always 0.

Only the first 100 messages of id 'CL189' are reported. To see all messages use 'report_messages -log D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\impl1\synlog\prox_detect_impl1_compiler.srr -id CL189' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {CL189} -count unlimited' in the Tcl shell.
Finished optimization stage 1 on segment_scan (CPU Time 0h:00m:00s, Memory Used current: 109MB peak: 140MB)
@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\prox_detect.v:18:7:18:18:@N:CG364:@XP_MSG">prox_detect.v(18)</a><!@TM:1741115669> | Synthesizing module prox_detect in library work.
Running optimization stage 1 on prox_detect .......
Finished optimization stage 1 on prox_detect (CPU Time 0h:00m:00s, Memory Used current: 109MB peak: 140MB)
Running optimization stage 2 on prox_detect .......
Finished optimization stage 2 on prox_detect (CPU Time 0h:00m:00s, Memory Used current: 108MB peak: 140MB)
Running optimization stage 2 on segment_scan .......
<font color=#A52A2A>@W:<a href="@W:CL190:@XP_HELP">CL190</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:72:0:72:6:@W:CL190:@XP_MSG">segment_scan.v(72)</a><!@TM:1741115669> | Optimizing register bit cnt[9] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:CL260:@XP_HELP">CL260</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:72:0:72:6:@W:CL260:@XP_MSG">segment_scan.v(72)</a><!@TM:1741115669> | Pruning register bit 9 of cnt[9:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.</font>
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:91:0:91:6:@N:CL201:@XP_MSG">segment_scan.v(91)</a><!@TM:1741115669> | Trying to extract state machine for register state.
Extracted state machine for register state
State machine has 3 reachable states with original encodings of:
   000
   001
   010
<font color=#A52A2A>@W:<a href="@W:CL249:@XP_HELP">CL249</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\segment_scan.v:91:0:91:6:@W:CL249:@XP_MSG">segment_scan.v(91)</a><!@TM:1741115669> | Initial value is not supported on state machine state</font>
Finished optimization stage 2 on segment_scan (CPU Time 0h:00m:00s, Memory Used current: 111MB peak: 140MB)
Running optimization stage 2 on decoder .......
Finished optimization stage 2 on decoder (CPU Time 0h:00m:00s, Memory Used current: 114MB peak: 140MB)
Running optimization stage 2 on bin_to_bcd .......
<font color=#A52A2A>@W:<a href="@W:CL247:@XP_HELP">CL247</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\bin_to_bcd.v:21:16:21:24:@W:CL247:@XP_MSG">bin_to_bcd.v(21)</a><!@TM:1741115669> | Input port bit 0 of bin_code[31:0] is unused</font>

Finished optimization stage 2 on bin_to_bcd (CPU Time 0h:00m:03s, Memory Used current: 132MB peak: 140MB)
Running optimization stage 2 on rpr0521rs_driver .......
<font color=#A52A2A>@W:<a href="@W:CL190:@XP_HELP">CL190</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@W:CL190:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115669> | Optimizing register bit cnt_mode1[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:CL190:@XP_HELP">CL190</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@W:CL190:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115669> | Optimizing register bit cnt_start[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:CL190:@XP_HELP">CL190</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@W:CL190:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115669> | Optimizing register bit cnt_stop[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:CL190:@XP_HELP">CL190</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@W:CL190:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115669> | Optimizing register bit cnt_read[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:CL190:@XP_HELP">CL190</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@W:CL190:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115669> | Optimizing register bit cnt_write[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:CL190:@XP_HELP">CL190</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@W:CL190:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115669> | Optimizing register bit cnt[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:CL260:@XP_HELP">CL260</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@W:CL260:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115669> | Pruning register bit 3 of cnt[3:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.</font>
<font color=#A52A2A>@W:<a href="@W:CL260:@XP_HELP">CL260</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@W:CL260:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115669> | Pruning register bit 3 of cnt_write[3:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.</font>
<font color=#A52A2A>@W:<a href="@W:CL260:@XP_HELP">CL260</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@W:CL260:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115669> | Pruning register bit 3 of cnt_read[3:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.</font>
<font color=#A52A2A>@W:<a href="@W:CL260:@XP_HELP">CL260</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@W:CL260:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115669> | Pruning register bit 3 of cnt_stop[3:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.</font>
<font color=#A52A2A>@W:<a href="@W:CL260:@XP_HELP">CL260</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@W:CL260:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115669> | Pruning register bit 3 of cnt_start[3:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.</font>
<font color=#A52A2A>@W:<a href="@W:CL260:@XP_HELP">CL260</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@W:CL260:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115669> | Pruning register bit 3 of cnt_mode1[3:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.</font>
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@N:CL201:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115669> | Trying to extract state machine for register state.
Extracted state machine for register state
State machine has 9 reachable states with original encodings of:
   0000
   0001
   0010
   0011
   0100
   0101
   0110
   0111
   1000
<font color=#A52A2A>@W:<a href="@W:CL260:@XP_HELP">CL260</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@W:CL260:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115669> | Pruning register bit 5 of data_wr[7:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.</font>
<font color=#A52A2A>@W:<a href="@W:CL260:@XP_HELP">CL260</a> : <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@W:CL260:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115669> | Pruning register bit 7 of reg_data[7:6]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.</font>
Finished optimization stage 2 on rpr0521rs_driver (CPU Time 0h:00m:00s, Memory Used current: 125MB peak: 140MB)

For a summary of runtime per design unit, please see file:
==========================================================
Linked File:  <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\impl1\synwork\layer0.duruntime:@XP_FILE">layer0.duruntime</a>



At c_ver Exit (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 126MB peak: 140MB)

Process took 0h:00m:08s realtime, 0h:00m:07s cputime

Process completed successfully.
# Wed Mar  5 03:14:29 2025

###########################################################]
###########################################################[

Copyright (C) 1994-2023 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: U-2023.03L-SP1
Install: C:\lscc\diamond\3.13\synpbase
OS: Windows 10 or later
Hostname: DESKTOP-L92NLN5

Implementation : impl1
<a name=compilerReport3></a>Synopsys Synopsys Netlist Linker, Version comp202303synp1, Build 155R, Built Aug 10 2023 09:42:17, @</a>

@N: : <!@TM:1741115669> | Running in 64-bit mode 
File D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\impl1\synwork\layer0.srs changed - recompiling
@N:<a href="@N:NF107:@XP_HELP">NF107</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\prox_detect.v:18:7:18:18:@N:NF107:@XP_MSG">prox_detect.v(18)</a><!@TM:1741115669> | Selected library: work cell: prox_detect view verilog as top level
@N:<a href="@N:NF107:@XP_HELP">NF107</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\prox_detect.v:18:7:18:18:@N:NF107:@XP_MSG">prox_detect.v(18)</a><!@TM:1741115669> | Selected library: work cell: prox_detect view verilog as top level

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 93MB peak: 93MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Wed Mar  5 03:14:29 2025

###########################################################]

For a summary of runtime and memory usage for all design units, please see file:
==========================================================
Linked File:  <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\impl1\synwork\prox_detect_impl1_comp.rt.csv:@XP_FILE">prox_detect_impl1_comp.rt.csv</a>

@END

At c_hdl Exit (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 24MB peak: 24MB)

Process took 0h:00m:08s realtime, 0h:00m:08s cputime

Process completed successfully.
# Wed Mar  5 03:14:29 2025

###########################################################]

</pre></samp></body></html>
<html><body><samp><pre>
<!@TC:1741115661>
###########################################################[

Copyright (C) 1994-2023 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: U-2023.03L-SP1
Install: C:\lscc\diamond\3.13\synpbase
OS: Windows 10 or later
Hostname: DESKTOP-L92NLN5

Implementation : impl1
<a name=compilerReport10></a>Synopsys Synopsys Netlist Linker, Version comp202303synp1, Build 155R, Built Aug 10 2023 09:42:17, @</a>

@N: : <!@TM:1741115671> | Running in 64-bit mode 
File D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\impl1\synwork\prox_detect_impl1_comp.srs changed - recompiling
@N:<a href="@N:NF107:@XP_HELP">NF107</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\prox_detect.v:18:7:18:18:@N:NF107:@XP_MSG">prox_detect.v(18)</a><!@TM:1741115671> | Selected library: work cell: prox_detect view verilog as top level
@N:<a href="@N:NF107:@XP_HELP">NF107</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\prox_detect.v:18:7:18:18:@N:NF107:@XP_MSG">prox_detect.v(18)</a><!@TM:1741115671> | Selected library: work cell: prox_detect view verilog as top level

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 93MB peak: 94MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Wed Mar  5 03:14:31 2025

###########################################################]

</pre></samp></body></html>
<html><body><samp><pre>
<!@TC:1741115661>
# Wed Mar  5 03:14:31 2025


Copyright (C) 1994-2023 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: U-2023.03L-SP1
Install: C:\lscc\diamond\3.13\synpbase
OS: Windows 10 or later
Hostname: DESKTOP-L92NLN5

Implementation : impl1
<a name=mapperReport17></a>Synopsys Lattice Technology Pre-mapping, Version map202303lat, Build 132R, Built Aug 31 2023 04:16:35, @</a>


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 123MB peak: 123MB)


Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 137MB)

@A:<a href="@A:MF827:@XP_HELP">MF827</a> : <!@TM:1741115674> | No constraint file specified. 
Linked File:  <a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\impl1\prox_detect_impl1_scck.rpt:@XP_FILE">prox_detect_impl1_scck.rpt</a>
See clock summary report "D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\impl1\prox_detect_impl1_scck.rpt"
@N:<a href="@N:MF916:@XP_HELP">MF916</a> : <!@TM:1741115674> | Option synthesis_strategy=base is enabled.  
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1741115674> | Running in 64-bit mode. 
@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1741115674> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 137MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 137MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 147MB peak: 148MB)

NConnInternalConnection caching is on
@N:<a href="@N:FX493:@XP_HELP">FX493</a> : <!@TM:1741115674> | Applying initial value "0" on instance clk_40khz. 
<font color=#A52A2A>@W:<a href="@W:FX474:@XP_HELP">FX474</a> : <!@TM:1741115674> | User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. </font> 

Starting HSTDM IP insertion (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 197MB peak: 197MB)


Finished HSTDM IP insertion (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 197MB peak: 197MB)


Started DisTri Cleanup (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 197MB peak: 197MB)


Finished DisTri Cleanup (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 197MB peak: 198MB)

Encoding state machine state[8:0] (in view: work.rpr0521rs_driver(verilog))
original code -> new code
   0000 -> 000000001
   0001 -> 000000010
   0010 -> 000000100
   0011 -> 000001000
   0100 -> 000010000
   0101 -> 000100000
   0110 -> 001000000
   0111 -> 010000000
   1000 -> 100000000
Encoding state machine state[2:0] (in view: work.segment_scan(verilog))
original code -> new code
   000 -> 00
   001 -> 01
   010 -> 10

Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 201MB peak: 201MB)


mixed edge conversion for GCC is OFF
@N:<a href="@N:MF578:@XP_HELP">MF578</a> : <!@TM:1741115674> | Incompatible asynchronous control logic preventing generated clock conversion. 
<font color=#A52A2A>@W:<a href="@W:BZ240:@XP_HELP">BZ240</a> : <!@TM:1741115674> | GCC encountered Inferred Clock constraint on net GCC considers to be data u4.clk_40khz; this will likely lead to failure to convert</font> 
<font color=#A52A2A>@W:<a href="@W:BZ240:@XP_HELP">BZ240</a> : <!@TM:1741115674> | GCC encountered Inferred Clock constraint on net GCC considers to be data u1.clk_400khz; this will likely lead to failure to convert</font> 
<font color=#A52A2A>@W:<a href="@W:BZ240:@XP_HELP">BZ240</a> : <!@TM:1741115674> | GCC encountered Inferred Clock constraint on net GCC considers to be data u1.dat_valid; this will likely lead to failure to convert</font> 

Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 202MB peak: 202MB)


Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 202MB peak: 202MB)


Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 202MB peak: 202MB)

@N:<a href="@N:FX1184:@XP_HELP">FX1184</a> : <!@TM:1741115674> | Applying syn_allowed_resources blockrams=10 on top level netlist prox_detect  

Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 202MB peak: 203MB)



<a name=mapperReport18></a>Clock Summary</a>
******************

          Start                                            Requested     Requested     Clock                                                        Clock          Clock
Level     Clock                                            Frequency     Period        Type                                                         Group          Load 
------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0 -       prox_detect|clk                                  200.0 MHz     5.000         inferred                                                     (multiple)     38   
1 .         rpr0521rs_driver|clk_400khz_derived_clock      200.0 MHz     5.000         derived (from prox_detect|clk)                               (multiple)     180  
2 ..          rpr0521rs_driver|dat_valid_derived_clock     200.0 MHz     5.000         derived (from rpr0521rs_driver|clk_400khz_derived_clock)     (multiple)     35   
1 .         segment_scan|clk_40khz_derived_clock           200.0 MHz     5.000         derived (from prox_detect|clk)                               (multiple)     30   
========================================================================================================================================================================



Clock Load Summary
***********************

                                              Clock     Source                        Clock Pin                Non-clock Pin     Non-clock Pin
Clock                                         Load      Pin                           Seq Example              Seq Example       Comb Example 
----------------------------------------------------------------------------------------------------------------------------------------------
prox_detect|clk                               38        clk(port)                     u4.cnt[8:0].C            -                 -            
rpr0521rs_driver|clk_400khz_derived_clock     180       u1.clk_400khz.Q[0](dffre)     u1.num_delay[23:0].C     -                 -            
rpr0521rs_driver|dat_valid_derived_clock      35        u1.dat_valid.Q[0](dffe)       u2.prox_dat0[15:0].C     -                 -            
segment_scan|clk_40khz_derived_clock          30        u4.clk_40khz.Q[0](dffr)       u4.seg_sck.C             -                 -            
==============================================================================================================================================

<font color=#A52A2A>@W:<a href="@W:MT529:@XP_HELP">MT529</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\rpr0521rs_driver.v:49:1:49:7:@W:MT529:@XP_MSG">rpr0521rs_driver.v(49)</a><!@TM:1741115674> | Found inferred clock prox_detect|clk which controls 38 sequential elements including u1.cnt_400khz[9:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. </font>

ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed:	0


@S |Clock Optimization Summary



<a name=clockReport19></a>#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[</a>

1 non-gated/non-generated clock tree(s) driving 38 clock pin(s) of sequential element(s)
3 gated/generated clock tree(s) driving 245 clock pin(s) of sequential element(s)
0 instances converted, 245 sequential instances remain driven by gated/generated clocks

=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
---------------------------------------------------------------------------------------
<a href="@|L:D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\impl1\synwork\prox_detect_impl1_prem.srm@|S:clk@|E:u4.clk_40khz@|F:@syn_dgcc_clockid0_2==1@|M:ClockId_0_2 @XP_NAMES_BY_PROP">ClockId_0_2</a>       clk                 port                   38         u4.clk_40khz   
=======================================================================================
================================================================ Gated/Generated Clocks ================================================================
Clock Tree ID     Driving Element        Drive Element Type     Unconverted Fanout     Sample Instance        Explanation                               
--------------------------------------------------------------------------------------------------------------------------------------------------------
<a href="@|L:D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\impl1\synwork\prox_detect_impl1_prem.srm@|S:u4.clk_40khz.Q[0]@|E:u4.state[1]@|F:@syn_dgcc_clockid0_0==1@|M:ClockId_0_0 @XP_NAMES_BY_PROP">ClockId_0_0</a>       u4.clk_40khz.Q[0]      dffr                   30                     u4.state[1]            Derived clock on input (not legal for GCC)
<a href="@|L:D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\impl1\synwork\prox_detect_impl1_prem.srm@|S:u1.dat_valid.Q[0]@|E:u2.prox_dat2[11:9]@|F:@syn_dgcc_clockid0_3==1@|M:ClockId_0_3 @XP_NAMES_BY_PROP">ClockId_0_3</a>       u1.dat_valid.Q[0]      dffe                   35                     u2.prox_dat2[11:9]     Derived clock on input (not legal for GCC)
<a href="@|L:D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\impl1\synwork\prox_detect_impl1_prem.srm@|S:u1.clk_400khz.Q[0]@|E:u1.state[8]@|F:@syn_dgcc_clockid0_5==1@|M:ClockId_0_5 @XP_NAMES_BY_PROP">ClockId_0_5</a>       u1.clk_400khz.Q[0]     dffre                  180                    u1.state[8]            Derived clock on input (not legal for GCC)
========================================================================================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######


Summary of user generated gated clocks:
0 user generated gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)

@N:<a href="@N:FX1143:@XP_HELP">FX1143</a> : <!@TM:1741115674> | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. 
Finished Pre Mapping Phase.

Starting constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 202MB peak: 203MB)


Finished constraint checker preprocessing (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 202MB peak: 203MB)


Finished constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 203MB peak: 203MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 117MB peak: 204MB)

Process took 0h:00m:02s realtime, 0h:00m:02s cputime
# Wed Mar  5 03:14:34 2025

###########################################################]

</pre></samp></body></html>
<html><body><samp><pre>
<!@TC:1741115661>
# Wed Mar  5 03:14:34 2025


Copyright (C) 1994-2023 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: U-2023.03L-SP1
Install: C:\lscc\diamond\3.13\synpbase
OS: Windows 10 or later
Hostname: DESKTOP-L92NLN5

Implementation : impl1
<a name=mapperReport26></a>Synopsys Lattice Technology Mapper, Version map202303lat, Build 132R, Built Aug 31 2023 04:16:35, @</a>


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 123MB peak: 123MB)

@N:<a href="@N:MF916:@XP_HELP">MF916</a> : <!@TM:1741115800> | Option synthesis_strategy=base is enabled.  
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1741115800> | Running in 64-bit mode. 
@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1741115800> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 137MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 137MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 139MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 195MB peak: 195MB)

@N:<a href="@N:BZ173:@XP_HELP">BZ173</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\segment_scan.v:116:32:116:43:@N:BZ173:@XP_MSG">segment_scan.v(116)</a><!@TM:1741115800> | ROM data_9[14:8] (in view: work.segment_scan(verilog)) mapped in logic.
@N:<a href="@N:BZ173:@XP_HELP">BZ173</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\segment_scan.v:115:32:115:43:@N:BZ173:@XP_MSG">segment_scan.v(115)</a><!@TM:1741115800> | ROM data_8[14:8] (in view: work.segment_scan(verilog)) mapped in logic.
@N:<a href="@N:BZ173:@XP_HELP">BZ173</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\segment_scan.v:114:32:114:43:@N:BZ173:@XP_MSG">segment_scan.v(114)</a><!@TM:1741115800> | ROM data_7[14:8] (in view: work.segment_scan(verilog)) mapped in logic.
@N:<a href="@N:BZ173:@XP_HELP">BZ173</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\segment_scan.v:113:32:113:43:@N:BZ173:@XP_MSG">segment_scan.v(113)</a><!@TM:1741115800> | ROM data_6[14:8] (in view: work.segment_scan(verilog)) mapped in logic.
@N:<a href="@N:BZ173:@XP_HELP">BZ173</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\segment_scan.v:112:32:112:43:@N:BZ173:@XP_MSG">segment_scan.v(112)</a><!@TM:1741115800> | ROM data_5[14:8] (in view: work.segment_scan(verilog)) mapped in logic.
@N:<a href="@N:BZ173:@XP_HELP">BZ173</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\segment_scan.v:111:32:111:43:@N:BZ173:@XP_MSG">segment_scan.v(111)</a><!@TM:1741115800> | ROM data_4[14:8] (in view: work.segment_scan(verilog)) mapped in logic.
@N:<a href="@N:BZ173:@XP_HELP">BZ173</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\segment_scan.v:110:32:110:43:@N:BZ173:@XP_MSG">segment_scan.v(110)</a><!@TM:1741115800> | ROM data_3[14:8] (in view: work.segment_scan(verilog)) mapped in logic.
@N:<a href="@N:BZ173:@XP_HELP">BZ173</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\segment_scan.v:109:32:109:43:@N:BZ173:@XP_MSG">segment_scan.v(109)</a><!@TM:1741115800> | ROM data_2[14:8] (in view: work.segment_scan(verilog)) mapped in logic.
@N:<a href="@N:BZ173:@XP_HELP">BZ173</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\segment_scan.v:116:32:116:43:@N:BZ173:@XP_MSG">segment_scan.v(116)</a><!@TM:1741115800> | ROM data_9[14:8] (in view: work.segment_scan(verilog)) mapped in logic.
@N:<a href="@N:MO106:@XP_HELP">MO106</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\segment_scan.v:116:32:116:43:@N:MO106:@XP_MSG">segment_scan.v(116)</a><!@TM:1741115800> | Found ROM data_9[14:8] (in view: work.segment_scan(verilog)) with 16 words by 7 bits.
@N:<a href="@N:BZ173:@XP_HELP">BZ173</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\segment_scan.v:115:32:115:43:@N:BZ173:@XP_MSG">segment_scan.v(115)</a><!@TM:1741115800> | ROM data_8[14:8] (in view: work.segment_scan(verilog)) mapped in logic.
@N:<a href="@N:MO106:@XP_HELP">MO106</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\segment_scan.v:115:32:115:43:@N:MO106:@XP_MSG">segment_scan.v(115)</a><!@TM:1741115800> | Found ROM data_8[14:8] (in view: work.segment_scan(verilog)) with 16 words by 7 bits.
@N:<a href="@N:BZ173:@XP_HELP">BZ173</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\segment_scan.v:114:32:114:43:@N:BZ173:@XP_MSG">segment_scan.v(114)</a><!@TM:1741115800> | ROM data_7[14:8] (in view: work.segment_scan(verilog)) mapped in logic.
@N:<a href="@N:MO106:@XP_HELP">MO106</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\segment_scan.v:114:32:114:43:@N:MO106:@XP_MSG">segment_scan.v(114)</a><!@TM:1741115800> | Found ROM data_7[14:8] (in view: work.segment_scan(verilog)) with 16 words by 7 bits.
@N:<a href="@N:BZ173:@XP_HELP">BZ173</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\segment_scan.v:113:32:113:43:@N:BZ173:@XP_MSG">segment_scan.v(113)</a><!@TM:1741115800> | ROM data_6[14:8] (in view: work.segment_scan(verilog)) mapped in logic.
@N:<a href="@N:MO106:@XP_HELP">MO106</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\segment_scan.v:113:32:113:43:@N:MO106:@XP_MSG">segment_scan.v(113)</a><!@TM:1741115800> | Found ROM data_6[14:8] (in view: work.segment_scan(verilog)) with 16 words by 7 bits.
@N:<a href="@N:BZ173:@XP_HELP">BZ173</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\segment_scan.v:112:32:112:43:@N:BZ173:@XP_MSG">segment_scan.v(112)</a><!@TM:1741115800> | ROM data_5[14:8] (in view: work.segment_scan(verilog)) mapped in logic.
@N:<a href="@N:MO106:@XP_HELP">MO106</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\segment_scan.v:112:32:112:43:@N:MO106:@XP_MSG">segment_scan.v(112)</a><!@TM:1741115800> | Found ROM data_5[14:8] (in view: work.segment_scan(verilog)) with 16 words by 7 bits.
@N:<a href="@N:BZ173:@XP_HELP">BZ173</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\segment_scan.v:111:32:111:43:@N:BZ173:@XP_MSG">segment_scan.v(111)</a><!@TM:1741115800> | ROM data_4[14:8] (in view: work.segment_scan(verilog)) mapped in logic.
@N:<a href="@N:MO106:@XP_HELP">MO106</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\segment_scan.v:111:32:111:43:@N:MO106:@XP_MSG">segment_scan.v(111)</a><!@TM:1741115800> | Found ROM data_4[14:8] (in view: work.segment_scan(verilog)) with 16 words by 7 bits.
@N:<a href="@N:BZ173:@XP_HELP">BZ173</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\segment_scan.v:110:32:110:43:@N:BZ173:@XP_MSG">segment_scan.v(110)</a><!@TM:1741115800> | ROM data_3[14:8] (in view: work.segment_scan(verilog)) mapped in logic.
@N:<a href="@N:MO106:@XP_HELP">MO106</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\segment_scan.v:110:32:110:43:@N:MO106:@XP_MSG">segment_scan.v(110)</a><!@TM:1741115800> | Found ROM data_3[14:8] (in view: work.segment_scan(verilog)) with 16 words by 7 bits.
@N:<a href="@N:BZ173:@XP_HELP">BZ173</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\segment_scan.v:109:32:109:43:@N:BZ173:@XP_MSG">segment_scan.v(109)</a><!@TM:1741115800> | ROM data_2[14:8] (in view: work.segment_scan(verilog)) mapped in logic.
@N:<a href="@N:MO106:@XP_HELP">MO106</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\segment_scan.v:109:32:109:43:@N:MO106:@XP_MSG">segment_scan.v(109)</a><!@TM:1741115800> | Found ROM data_2[14:8] (in view: work.segment_scan(verilog)) with 16 words by 7 bits.

Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 207MB peak: 207MB)

<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@W:BN132:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115800> | Removing instance u1.num_delay[23] because it is equivalent to instance u1.num_delay[22]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@W:BN132:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115800> | Removing instance u1.num_delay[22] because it is equivalent to instance u1.num_delay[21]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@W:BN132:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115800> | Removing instance u1.num_delay[21] because it is equivalent to instance u1.num_delay[20]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@W:BN132:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115800> | Removing instance u1.num_delay[20] because it is equivalent to instance u1.num_delay[19]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@W:BN132:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115800> | Removing instance u1.num_delay[19] because it is equivalent to instance u1.num_delay[18]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@W:BN132:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115800> | Removing instance u1.num_delay[18] because it is equivalent to instance u1.num_delay[17]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@W:BN132:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115800> | Removing instance u1.num_delay[17] because it is equivalent to instance u1.num_delay[16]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@W:BN132:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115800> | Removing instance u1.num_delay[16] because it is equivalent to instance u1.num_delay[15]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@W:BN132:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115800> | Removing instance u1.num_delay[15] because it is equivalent to instance u1.num_delay[14]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@W:BN132:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115800> | Removing instance u1.num_delay[14] because it is equivalent to instance u1.num_delay[13]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@W:BN132:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115800> | Removing instance u1.num_delay[13] because it is equivalent to instance u1.num_delay[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@W:BN132:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115800> | Removing instance u1.num_delay[11] because it is equivalent to instance u1.num_delay[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@W:BN132:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115800> | Removing instance u1.num_delay[8] because it is equivalent to instance u1.num_delay[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@W:BN132:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115800> | Removing instance u1.num_delay[5] because it is equivalent to instance u1.num_delay[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@W:BN132:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115800> | Removing instance u1.num_delay[4] because it is equivalent to instance u1.num_delay[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@W:BN132:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115800> | Removing instance u1.num_delay[3] because it is equivalent to instance u1.num_delay[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@W:BN132:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115800> | Removing instance u1.num_delay[2] because it is equivalent to instance u1.num_delay[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@W:BN132:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115800> | Removing instance u1.num_delay[1] because it is equivalent to instance u1.num_delay[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@W:BN132:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115800> | Removing instance u1.num_delay[10] because it is equivalent to instance u1.num_delay[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@W:BN132:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115800> | Removing instance u1.reg_data[6] because it is equivalent to instance u1.reg_data[2]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@W:BN132:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115800> | Removing instance u1.num_delay[9] because it is equivalent to instance u1.num_delay[12]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@W:BN132:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115800> | Removing instance u1.num_delay[7] because it is equivalent to instance u1.num_delay[12]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@W:BN132:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115800> | Removing instance u1.num_delay[6] because it is equivalent to instance u1.num_delay[12]. To keep the instance, apply constraint syn_preserve=1 on the instance.</font>
@N:<a href="@N:MO231:@XP_HELP">MO231</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@N:MO231:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115800> | Found counter in view:work.rpr0521rs_driver(verilog) instance cnt_delay[23:0] 
@N:<a href="@N:MO231:@XP_HELP">MO231</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@N:MO231:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115800> | Found counter in view:work.rpr0521rs_driver(verilog) instance cnt_mode2[3:0] 
@N:<a href="@N:MO231:@XP_HELP">MO231</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@N:MO231:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115800> | Found counter in view:work.rpr0521rs_driver(verilog) instance cnt_main[3:0] 
@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@N:BN362:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115800> | Removing sequential instance num_delay[0] (in view: work.rpr0521rs_driver(verilog)) because it does not drive other instances.
@N:<a href="@N:MO231:@XP_HELP">MO231</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\segment_scan.v:91:0:91:6:@N:MO231:@XP_MSG">segment_scan.v(91)</a><!@TM:1741115800> | Found counter in view:work.segment_scan(verilog) instance cnt_write[5:0] 
@N:<a href="@N:MO231:@XP_HELP">MO231</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\segment_scan.v:72:0:72:6:@N:MO231:@XP_MSG">segment_scan.v(72)</a><!@TM:1741115800> | Found counter in view:work.segment_scan(verilog) instance cnt[8:0] 

Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 211MB peak: 211MB)


Finished factoring (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 249MB peak: 250MB)


Available hyper_sources - for debug and ip models
	None Found

NConnInternalConnection caching is on

Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 229MB peak: 253MB)

@N:<a href="@N:FA113:@XP_HELP">FA113</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\decoder.v:63:1:63:3:@N:FA113:@XP_MSG">decoder.v(63)</a><!@TM:1741115800> | Pipelining module un1_lux_1[28:0]. For more information, search for "pipelining" in Online Help.
@N:<a href="@N:MF169:@XP_HELP">MF169</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@N:MF169:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115800> | Pushed in register ch0_dat[15:0].
@N:<a href="@N:MF169:@XP_HELP">MF169</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@N:MF169:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115800> | Pushed in register dat_l[7:0].
@N:<a href="@N:MF169:@XP_HELP">MF169</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@N:MF169:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115800> | Pushed in register dat_h[7:0].
@N:<a href="@N:MF169:@XP_HELP">MF169</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@N:MF169:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115800> | Pushed in register ch1_dat[15:0].
@N:<a href="@N:MF169:@XP_HELP">MF169</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@N:MF169:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115800> | Pushed in register prox_dat[15:0].
@N:<a href="@N:MF169:@XP_HELP">MF169</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@N:MF169:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115800> | Pushed in register data_r[7:0].
@N:<a href="@N:MF169:@XP_HELP">MF169</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\decoder.v:33:0:33:6:@N:MF169:@XP_MSG">decoder.v(33)</a><!@TM:1741115800> | Pushed in register prox_dat0[15:0].
@N:<a href="@N:MF169:@XP_HELP">MF169</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\decoder.v:33:0:33:6:@N:MF169:@XP_MSG">decoder.v(33)</a><!@TM:1741115800> | Pushed in register prox_dat1[15:0].
@N:<a href="@N:MF169:@XP_HELP">MF169</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\decoder.v:33:0:33:6:@N:MF169:@XP_MSG">decoder.v(33)</a><!@TM:1741115800> | Pushed in register prox_dat2[11:9].

Starting Early Timing Optimization (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 237MB peak: 253MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:44s; CPU Time elapsed 0h:00m:42s; Memory used current: 309MB peak: 309MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:44s; CPU Time elapsed 0h:00m:42s; Memory used current: 309MB peak: 310MB)

<font color=#A52A2A>@W:<a href="@W:FX474:@XP_HELP">FX474</a> : <!@TM:1741115800> | User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. </font> 

Finished preparing to map (Real Time elapsed 0h:00m:44s; CPU Time elapsed 0h:00m:43s; Memory used current: 310MB peak: 310MB)


Finished technology mapping (Real Time elapsed 0h:01m:50s; CPU Time elapsed 0h:01m:48s; Memory used current: 349MB peak: 527MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:01m:49s		   -74.28ns		1482 /       546
   2		0h:01m:49s		   -73.10ns		1458 /       546
   3		0h:01m:49s		   -72.09ns		1458 /       546
   4		0h:01m:49s		   -71.24ns		1459 /       546
   5		0h:01m:49s		   -71.54ns		1459 /       546
   6		0h:01m:49s		   -71.54ns		1461 /       546
   7		0h:01m:50s		   -71.54ns		1460 /       546
   8		0h:01m:50s		   -71.54ns		1461 /       546
@N:<a href="@N:FX271:@XP_HELP">FX271</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@N:FX271:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115800> | Replicating instance u1.ch0_dat[0] (in view: work.prox_detect(verilog)) with 38 loads 3 times to improve timing.
@N:<a href="@N:FX271:@XP_HELP">FX271</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@N:FX271:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115800> | Replicating instance u1.ch0_dat[1] (in view: work.prox_detect(verilog)) with 26 loads 2 times to improve timing.
@N:<a href="@N:FX271:@XP_HELP">FX271</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@N:FX271:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115800> | Replicating instance u1.ch0_dat[2] (in view: work.prox_detect(verilog)) with 25 loads 2 times to improve timing.
@N:<a href="@N:FX271:@XP_HELP">FX271</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@N:FX271:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115800> | Replicating instance u1.ch0_dat[3] (in view: work.prox_detect(verilog)) with 17 loads 2 times to improve timing.
@N:<a href="@N:FX271:@XP_HELP">FX271</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@N:FX271:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115800> | Replicating instance u1.ch0_dat[4] (in view: work.prox_detect(verilog)) with 16 loads 2 times to improve timing.
@N:<a href="@N:FX271:@XP_HELP">FX271</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@N:FX271:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115800> | Replicating instance u1.ch0_dat[5] (in view: work.prox_detect(verilog)) with 15 loads 2 times to improve timing.
@N:<a href="@N:FX271:@XP_HELP">FX271</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@N:FX271:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115800> | Replicating instance u1.ch0_dat[6] (in view: work.prox_detect(verilog)) with 16 loads 2 times to improve timing.
@N:<a href="@N:FX271:@XP_HELP">FX271</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@N:FX271:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115800> | Replicating instance u1.ch0_dat[8] (in view: work.prox_detect(verilog)) with 15 loads 2 times to improve timing.
@N:<a href="@N:FX271:@XP_HELP">FX271</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@N:FX271:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115800> | Replicating instance u1.ch1_dat[0] (in view: work.prox_detect(verilog)) with 18 loads 2 times to improve timing.
@N:<a href="@N:FX271:@XP_HELP">FX271</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@N:FX271:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115800> | Replicating instance u1.ch1_dat[5] (in view: work.prox_detect(verilog)) with 17 loads 2 times to improve timing.
@N:<a href="@N:FX271:@XP_HELP">FX271</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@N:FX271:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115800> | Replicating instance u1.ch1_dat[4] (in view: work.prox_detect(verilog)) with 16 loads 2 times to improve timing.
@N:<a href="@N:FX271:@XP_HELP">FX271</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@N:FX271:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115800> | Replicating instance u1.ch1_dat[6] (in view: work.prox_detect(verilog)) with 15 loads 2 times to improve timing.
Timing driven replication report
Added 25 Registers via timing driven replication
Added 0 LUTs via timing driven replication

   9		0h:01m:53s		   -71.31ns		1462 /       571
  10		0h:01m:53s		   -67.81ns		1479 /       571
  11		0h:01m:53s		   -67.24ns		1480 /       571
  12		0h:01m:53s		   -65.63ns		1482 /       571
  13		0h:01m:54s		   -65.65ns		1485 /       571
  14		0h:01m:54s		   -65.21ns		1486 /       571
  15		0h:01m:54s		   -65.24ns		1487 /       571
  16		0h:01m:54s		   -65.83ns		1488 /       571
  17		0h:01m:54s		   -64.92ns		1490 /       571

  18		0h:01m:54s		   -64.34ns		1486 /       571
  19		0h:01m:54s		   -63.80ns		1489 /       571
  20		0h:01m:55s		   -63.25ns		1490 /       571
  21		0h:01m:55s		   -62.82ns		1498 /       571
  22		0h:01m:55s		   -61.37ns		1499 /       571
  23		0h:01m:55s		   -62.25ns		1504 /       571
  24		0h:01m:56s		   -61.78ns		1505 /       571
  25		0h:01m:56s		   -61.09ns		1506 /       571
  26		0h:01m:56s		   -61.05ns		1511 /       571
  27		0h:01m:56s		   -60.57ns		1516 /       571
  28		0h:01m:56s		   -60.39ns		1517 /       571
  29		0h:01m:56s		   -60.14ns		1521 /       571
  30		0h:01m:56s		   -59.43ns		1522 /       571
  31		0h:01m:56s		   -59.41ns		1526 /       571
  32		0h:01m:56s		   -59.01ns		1526 /       571
  33		0h:01m:57s		   -58.90ns		1526 /       571
  34		0h:01m:57s		   -58.42ns		1534 /       571
  35		0h:01m:57s		   -58.44ns		1534 /       571
  36		0h:01m:57s		   -58.18ns		1542 /       571
  37		0h:01m:58s		   -58.06ns		1548 /       571
  38		0h:01m:58s		   -57.28ns		1548 /       571
  39		0h:01m:58s		   -56.62ns		1555 /       571
  40		0h:01m:58s		   -57.12ns		1558 /       571
  41		0h:01m:58s		   -56.72ns		1558 /       571
  42		0h:01m:59s		   -57.14ns		1562 /       571
  43		0h:01m:59s		   -56.94ns		1562 /       571

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:02m:01s; CPU Time elapsed 0h:01m:59s; Memory used current: 307MB peak: 527MB)

@N:<a href="@N:BN362:@XP_HELP">BN362</a> : <a href="d:\baidunetdiskdownload\v4.0\lab8_prox_detect\source\rpr0521rs_driver.v:70:1:70:7:@N:BN362:@XP_MSG">rpr0521rs_driver.v(70)</a><!@TM:1741115800> | Removing sequential instance u1.num_delay[12] (in view: work.prox_detect(verilog)) because it does not drive other instances.
@N:<a href="@N:FX164:@XP_HELP">FX164</a> : <!@TM:1741115800> | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   

Warning: Forcing use of GSR for flip-flops and
latches that do not specify sets or resets
   u1.ch0_dat[15] (in view: work.prox_detect(verilog))
   u1.ch0_dat[14] (in view: work.prox_detect(verilog))
   u1.ch0_dat[13] (in view: work.prox_detect(verilog))
   u1.ch0_dat[12] (in view: work.prox_detect(verilog))
   u1.ch0_dat[11] (in view: work.prox_detect(verilog))
   u1.ch0_dat[10] (in view: work.prox_detect(verilog))
   u1.ch0_dat[9] (in view: work.prox_detect(verilog))
   u1.ch0_dat[8] (in view: work.prox_detect(verilog))
   u1.ch0_dat_fast[8] (in view: work.prox_detect(verilog))
   u1.ch0_dat[7] (in view: work.prox_detect(verilog))
   u1.ch0_dat[6] (in view: work.prox_detect(verilog))
   u1.ch0_dat[5] (in view: work.prox_detect(verilog))
   u1.ch0_dat[4] (in view: work.prox_detect(verilog))
   u1.ch0_dat[2] (in view: work.prox_detect(verilog))
   u1.ch0_dat[0] (in view: work.prox_detect(verilog))
   u1.ch0_dat_0_rep2 (in view: work.prox_detect(verilog))
   u1.ch0_dat_1_rep1 (in view: work.prox_detect(verilog))
   u1.ch0_dat_2_rep1 (in view: work.prox_detect(verilog))
   u1.ch0_dat_3_rep1 (in view: work.prox_detect(verilog))
   u1.ch0_dat_4_rep1 (in view: work.prox_detect(verilog))
   u1.ch0_dat_5_rep1 (in view: work.prox_detect(verilog))
   u1.ch0_dat_8_rep1 (in view: work.prox_detect(verilog))
   u1.ch0_dat_fast[6] (in view: work.prox_detect(verilog))
   u1.ch0_dat_fast[5] (in view: work.prox_detect(verilog))
   u1.ch0_dat_fast[4] (in view: work.prox_detect(verilog))
   u1.ch0_dat_fast[3] (in view: work.prox_detect(verilog))
   u1.ch0_dat[3] (in view: work.prox_detect(verilog))
   u1.ch0_dat[1] (in view: work.prox_detect(verilog))
   u1.ch0_dat_0_rep1 (in view: work.prox_detect(verilog))
   u1.ch0_dat_6_rep1 (in view: work.prox_detect(verilog))
   u1.ch0_dat_fast[2] (in view: work.prox_detect(verilog))
   u1.ch0_dat_fast[1] (in view: work.prox_detect(verilog))
   u1.ch0_dat_fast[0] (in view: work.prox_detect(verilog))
   u1.ch1_dat[15] (in view: work.prox_detect(verilog))
   u1.ch1_dat[14] (in view: work.prox_detect(verilog))
   u1.ch1_dat[13] (in view: work.prox_detect(verilog))
   u1.ch1_dat[12] (in view: work.prox_detect(verilog))
   u1.ch1_dat[11] (in view: work.prox_detect(verilog))
   u1.ch1_dat[10] (in view: work.prox_detect(verilog))
   u1.ch1_dat[9] (in view: work.prox_detect(verilog))
   u1.ch1_dat[8] (in view: work.prox_detect(verilog))
   u1.ch1_dat[7] (in view: work.prox_detect(verilog))
   u1.ch1_dat_fast[6] (in view: work.prox_detect(verilog))
   u1.ch1_dat[6] (in view: work.prox_detect(verilog))
   u1.ch1_dat[5] (in view: work.prox_detect(verilog))
   u1.ch1_dat[4] (in view: work.prox_detect(verilog))
   u1.ch1_dat[3] (in view: work.prox_detect(verilog))
   u1.ch1_dat[2] (in view: work.prox_detect(verilog))
   u1.ch1_dat[1] (in view: work.prox_detect(verilog))
   u1.ch1_dat_0_rep1 (in view: work.prox_detect(verilog))
   u1.ch1_dat_4_rep1 (in view: work.prox_detect(verilog))
   u1.ch1_dat_5_rep1 (in view: work.prox_detect(verilog))
   u1.ch1_dat_6_rep1 (in view: work.prox_detect(verilog))
   u1.ch1_dat_fast[5] (in view: work.prox_detect(verilog))
   u1.ch1_dat_fast[4] (in view: work.prox_detect(verilog))
   u1.ch1_dat_fast[0] (in view: work.prox_detect(verilog))
   u1.ch1_dat[0] (in view: work.prox_detect(verilog))
   u1.dat_h[7] (in view: work.prox_detect(verilog))
   u1.dat_h[6] (in view: work.prox_detect(verilog))
   u1.dat_h[5] (in view: work.prox_detect(verilog))
   u1.dat_h[4] (in view: work.prox_detect(verilog))
   u1.dat_h[3] (in view: work.prox_detect(verilog))
   u1.dat_h[2] (in view: work.prox_detect(verilog))
   u1.dat_h[1] (in view: work.prox_detect(verilog))
   u1.dat_h[0] (in view: work.prox_detect(verilog))
   u1.dat_l[7] (in view: work.prox_detect(verilog))
   u1.dat_l[6] (in view: work.prox_detect(verilog))
   u1.dat_l[5] (in view: work.prox_detect(verilog))
   u1.dat_l[4] (in view: work.prox_detect(verilog))
   u1.dat_l[3] (in view: work.prox_detect(verilog))
   u1.dat_l[2] (in view: work.prox_detect(verilog))
   u1.dat_l[1] (in view: work.prox_detect(verilog))
   u1.dat_l[0] (in view: work.prox_detect(verilog))
   u1.dat_valid (in view: work.prox_detect(verilog))
   u1.data_r[7] (in view: work.prox_detect(verilog))
   u1.data_r[6] (in view: work.prox_detect(verilog))
   u1.data_r[5] (in view: work.prox_detect(verilog))
   u1.data_r[4] (in view: work.prox_detect(verilog))
   u1.data_r[3] (in view: work.prox_detect(verilog))
   u1.data_r[2] (in view: work.prox_detect(verilog))
   u1.data_r[1] (in view: work.prox_detect(verilog))
   u1.data_r[0] (in view: work.prox_detect(verilog))
   u1.data_wr[7] (in view: work.prox_detect(verilog))
   u1.data_wr[6] (in view: work.prox_detect(verilog))
   u1.data_wr[4] (in view: work.prox_detect(verilog))
   u1.data_wr[3] (in view: work.prox_detect(verilog))
   u1.data_wr[2] (in view: work.prox_detect(verilog))
   u1.data_wr[1] (in view: work.prox_detect(verilog))
   u1.data_wr[0] (in view: work.prox_detect(verilog))
   u1.prox_dat[15] (in view: work.prox_detect(verilog))
   u1.prox_dat[14] (in view: work.prox_detect(verilog))
   u1.prox_dat[13] (in view: work.prox_detect(verilog))
   u1.prox_dat[12] (in view: work.prox_detect(verilog))
   u1.prox_dat[11] (in view: work.prox_detect(verilog))
   u1.prox_dat[10] (in view: work.prox_detect(verilog))
   u1.prox_dat[9] (in view: work.prox_detect(verilog))
   u1.prox_dat[8] (in view: work.prox_detect(verilog))
   u1.prox_dat[7] (in view: work.prox_detect(verilog))
   u1.prox_dat[6] (in view: work.prox_detect(verilog))
   u1.prox_dat[5] (in view: work.prox_detect(verilog))
   u1.prox_dat[4] (in view: work.prox_detect(verilog))
   u1.prox_dat[3] (in view: work.prox_detect(verilog))
   u1.prox_dat[2] (in view: work.prox_detect(verilog))
   u1.prox_dat[1] (in view: work.prox_detect(verilog))
   u1.prox_dat[0] (in view: work.prox_detect(verilog))
   u1.reg_addr[3] (in view: work.prox_detect(verilog))
   u1.reg_addr[2] (in view: work.prox_detect(verilog))
   u1.reg_addr[1] (in view: work.prox_detect(verilog))
   u1.reg_addr[0] (in view: work.prox_detect(verilog))
   u1.reg_data[3] (in view: work.prox_detect(verilog))
   u1.reg_data[2] (in view: work.prox_detect(verilog))
   u1.reg_data[1] (in view: work.prox_detect(verilog))
   u1.reg_data[0] (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_10 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_100 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_101 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_102 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_103 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_104 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_105 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_106 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_107 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_108 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_109 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_11 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_110 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_111 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_112 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_113 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_114 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_115 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_119 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_12 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_120 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_121 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_122 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_123 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_124 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_125 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_126 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_127 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_128 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_129 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_13 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_130 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_131 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_132 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_133 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_134 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_135 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_14 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_143 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_144 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_145 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_146 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_147 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_148 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_149 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_15 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_150 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_151 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_152 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_153 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_154 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_155 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_156 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_157 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_158 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_159 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_16 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_166 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_167 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_168 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_169 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_17 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_170 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_171 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_172 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_173 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_174 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_175 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_176 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_177 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_178 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_179 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_18 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_180 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_181 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_182 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_183 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_184 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_185 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_19 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_190 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_191 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_192 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_193 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_194 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_195 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_196 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_197 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_198 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_199 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_20 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_200 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_201 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_202 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_203 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_204 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_205 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_206 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_207 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_208 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_209 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_21 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_210 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_211 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_215 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_216 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_217 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_218 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_219 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_22 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_220 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_221 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_222 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_223 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_224 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_225 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_226 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_227 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_228 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_229 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_23 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_230 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_231 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_232 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_233 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_234 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_235 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_236 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_237 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_238 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_239 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_34 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_35 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_36 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_37 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_38 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_39 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_4 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_40 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_41 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_42 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_43 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_44 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_45 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_46 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_47 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_48 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_49 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_5 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_50 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_53 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_54 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_55 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_56 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_57 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_58 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_59 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_6 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_60 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_61 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_62 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_63 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_64 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_65 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_66 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_67 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_68 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_69 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_7 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_70 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_71 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_73 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_74 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_75 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_76 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_77 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_78 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_79 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_8 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_80 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_81 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_82 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_83 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_84 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_85 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_86 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_87 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_88 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_89 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_9 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_90 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_91 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_92 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_93 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_94 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_95 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_96 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_97 (in view: work.prox_detect(verilog))
   u2.ch0_dat_pipe_99 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_10 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_100 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_11 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_12 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_13 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_14 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_15 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_16 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_17 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_18 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_19 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_20 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_21 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_22 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_27 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_28 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_29 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_30 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_31 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_32 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_33 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_34 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_35 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_36 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_37 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_38 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_39 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_4 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_40 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_41 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_42 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_43 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_44 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_45 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_46 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_47 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_48 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_49 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_5 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_54 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_55 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_56 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_57 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_58 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_59 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_6 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_60 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_61 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_62 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_63 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_64 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_65 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_66 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_67 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_68 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_69 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_7 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_70 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_71 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_72 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_73 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_74 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_75 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_76 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_77 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_78 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_79 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_8 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_81 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_82 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_83 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_84 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_85 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_86 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_87 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_88 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_89 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_9 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_90 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_91 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_92 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_93 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_94 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_95 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_96 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_97 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_98 (in view: work.prox_detect(verilog))
   u2.ch1_dat_pipe_99 (in view: work.prox_detect(verilog))
   u2.prox_dat0[15] (in view: work.prox_detect(verilog))
   u2.prox_dat0[14] (in view: work.prox_detect(verilog))
   u2.prox_dat0[13] (in view: work.prox_detect(verilog))
   u2.prox_dat0[12] (in view: work.prox_detect(verilog))
   u2.prox_dat0[11] (in view: work.prox_detect(verilog))
   u2.prox_dat0[10] (in view: work.prox_detect(verilog))
   u2.prox_dat0[9] (in view: work.prox_detect(verilog))
   u2.prox_dat0[8] (in view: work.prox_detect(verilog))
   u2.prox_dat0[7] (in view: work.prox_detect(verilog))
   u2.prox_dat0[6] (in view: work.prox_detect(verilog))
   u2.prox_dat0[5] (in view: work.prox_detect(verilog))
   u2.prox_dat0[4] (in view: work.prox_detect(verilog))
   u2.prox_dat0[3] (in view: work.prox_detect(verilog))
   u2.prox_dat0[2] (in view: work.prox_detect(verilog))
   u2.prox_dat0[1] (in view: work.prox_detect(verilog))
   u2.prox_dat0[0] (in view: work.prox_detect(verilog))
   u2.prox_dat1[15] (in view: work.prox_detect(verilog))
   u2.prox_dat1[14] (in view: work.prox_detect(verilog))
   u2.prox_dat1[13] (in view: work.prox_detect(verilog))
   u2.prox_dat1[12] (in view: work.prox_detect(verilog))
   u2.prox_dat1[11] (in view: work.prox_detect(verilog))
   u2.prox_dat1[10] (in view: work.prox_detect(verilog))
   u2.prox_dat1[9] (in view: work.prox_detect(verilog))
   u2.prox_dat1[8] (in view: work.prox_detect(verilog))
   u2.prox_dat1[7] (in view: work.prox_detect(verilog))
   u2.prox_dat1[6] (in view: work.prox_detect(verilog))
   u2.prox_dat1[5] (in view: work.prox_detect(verilog))
   u2.prox_dat1[4] (in view: work.prox_detect(verilog))
   u2.prox_dat1[3] (in view: work.prox_detect(verilog))
   u2.prox_dat1[2] (in view: work.prox_detect(verilog))
   u2.prox_dat1[1] (in view: work.prox_detect(verilog))
   u2.prox_dat1[0] (in view: work.prox_detect(verilog))
   u2.prox_dat2[11] (in view: work.prox_detect(verilog))
   u2.prox_dat2[10] (in view: work.prox_detect(verilog))
   u2.prox_dat2[9] (in view: work.prox_detect(verilog))
   u4.data[15] (in view: work.prox_detect(verilog))
   u4.data[14] (in view: work.prox_detect(verilog))
   u4.data[13] (in view: work.prox_detect(verilog))
   u4.data[12] (in view: work.prox_detect(verilog))
   u4.data[11] (in view: work.prox_detect(verilog))
   u4.data[10] (in view: work.prox_detect(verilog))
   u4.data[9] (in view: work.prox_detect(verilog))
   u4.data[8] (in view: work.prox_detect(verilog))
   u4.data[7] (in view: work.prox_detect(verilog))
   u4.data[6] (in view: work.prox_detect(verilog))
   u4.data[5] (in view: work.prox_detect(verilog))
   u4.data[4] (in view: work.prox_detect(verilog))
   u4.data[3] (in view: work.prox_detect(verilog))
   u4.data[2] (in view: work.prox_detect(verilog))
   u4.data[1] (in view: work.prox_detect(verilog))
   u4.data[0] (in view: work.prox_detect(verilog))


Finished restoring hierarchy (Real Time elapsed 0h:02m:02s; CPU Time elapsed 0h:02m:00s; Memory used current: 310MB peak: 527MB)


Starting CDBProcessSetClockGroups... (Real Time elapsed 0h:02m:02s; CPU Time elapsed 0h:02m:00s; Memory used current: 310MB peak: 527MB)


Finished with CDBProcessSetClockGroups (Real Time elapsed 0h:02m:02s; CPU Time elapsed 0h:02m:00s; Memory used current: 311MB peak: 527MB)


Start Writing Netlists (Real Time elapsed 0h:02m:02s; CPU Time elapsed 0h:02m:01s; Memory used current: 235MB peak: 527MB)

Writing Analyst data base D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\impl1\synwork\prox_detect_impl1_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:02m:03s; CPU Time elapsed 0h:02m:01s; Memory used current: 298MB peak: 527MB)

Writing EDIF Netlist and constraint files
@N:<a href="@N:FX1056:@XP_HELP">FX1056</a> : <!@TM:1741115800> | Writing EDF file: D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\impl1\prox_detect_impl1.edi 
@N:<a href="@N:BW106:@XP_HELP">BW106</a> : <!@TM:1741115800> | Synplicity Constraint File capacitance units using default value of 1pF  

Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:02m:04s; CPU Time elapsed 0h:02m:02s; Memory used current: 307MB peak: 527MB)


Finished Writing Netlists (Real Time elapsed 0h:02m:04s; CPU Time elapsed 0h:02m:02s; Memory used current: 307MB peak: 527MB)


Start final timing analysis (Real Time elapsed 0h:02m:04s; CPU Time elapsed 0h:02m:03s; Memory used current: 294MB peak: 527MB)

<font color=#A52A2A>@W:<a href="@W:MT420:@XP_HELP">MT420</a> : <!@TM:1741115800> | Found inferred clock prox_detect|clk with period 5.00ns. Please declare a user-defined clock on port clk.</font> 
@N:<a href="@N:MT615:@XP_HELP">MT615</a> : <!@TM:1741115800> | Found clock rpr0521rs_driver|clk_400khz_derived_clock with period 5.00ns  
@N:<a href="@N:MT615:@XP_HELP">MT615</a> : <!@TM:1741115800> | Found clock segment_scan|clk_40khz_derived_clock with period 5.00ns  
@N:<a href="@N:MT615:@XP_HELP">MT615</a> : <!@TM:1741115800> | Found clock rpr0521rs_driver|dat_valid_derived_clock with period 5.00ns  


<a name=timingReport27></a>##### START OF TIMING REPORT #####[</a>
# Timing report written on Wed Mar  5 03:16:39 2025
#


Top view:               prox_detect
Requested Frequency:    200.0 MHz
Wire load mode:         top
Paths requested:        3
Constraint File(s):    
@N:<a href="@N:MT320:@XP_HELP">MT320</a> : <!@TM:1741115800> | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 

@N:<a href="@N:MT322:@XP_HELP">MT322</a> : <!@TM:1741115800> | Clock constraints include only register-to-register paths associated with each individual clock. 



<a name=performanceSummary28></a>Performance Summary</a>
*******************


Worst slack in design: -62.936

                                              Requested     Estimated     Requested     Estimated                 Clock                                                        Clock          
Starting Clock                                Frequency     Frequency     Period        Period        Slack       Type                                                         Group          
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
prox_detect|clk                               200.0 MHz     185.9 MHz     5.000         5.379         -0.379      inferred                                                     (multiple)     
rpr0521rs_driver|clk_400khz_derived_clock     200.0 MHz     14.7 MHz      5.000         67.936        -62.936     derived (from prox_detect|clk)                               (multiple)     
rpr0521rs_driver|dat_valid_derived_clock      200.0 MHz     261.9 MHz     5.000         3.818         2.365       derived (from rpr0521rs_driver|clk_400khz_derived_clock)     (multiple)     
segment_scan|clk_40khz_derived_clock          200.0 MHz     14.7 MHz      5.000         67.936        2.810       derived (from prox_detect|clk)                               (multiple)     
System                                        200.0 MHz     NA            5.000         NA            NA          system                                                       system_clkgroup
==============================================================================================================================================================================================
Estimated period and frequency reported as NA means no slack depends directly on the clock waveform





<a name=clockRelationships29></a>Clock Relationships</a>
*******************

Clocks                                                                                |    rise  to  rise     |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Starting                                   Ending                                     |  constraint  slack    |  constraint  slack  |  constraint  slack  |  constraint  slack
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
prox_detect|clk                            prox_detect|clk                            |  5.000       -0.379   |  No paths    -      |  No paths    -      |  No paths    -    
rpr0521rs_driver|clk_400khz_derived_clock  rpr0521rs_driver|clk_400khz_derived_clock  |  5.000       -1.570   |  No paths    -      |  No paths    -      |  No paths    -    
rpr0521rs_driver|clk_400khz_derived_clock  segment_scan|clk_40khz_derived_clock       |  5.000       -62.936  |  No paths    -      |  No paths    -      |  No paths    -    
rpr0521rs_driver|clk_400khz_derived_clock  rpr0521rs_driver|dat_valid_derived_clock   |  5.000       3.923    |  No paths    -      |  No paths    -      |  No paths    -    
segment_scan|clk_40khz_derived_clock       segment_scan|clk_40khz_derived_clock       |  5.000       2.810    |  No paths    -      |  No paths    -      |  No paths    -    
rpr0521rs_driver|dat_valid_derived_clock   rpr0521rs_driver|dat_valid_derived_clock   |  5.000       2.365    |  No paths    -      |  No paths    -      |  No paths    -    
==============================================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



<a name=interfaceInfo30></a>Interface Information </a>
*********************

No IO constraint found



====================================
<a name=clockReport31></a>Detailed Report for Clock: prox_detect|clk</a>
====================================



<a name=startingSlack32></a>Starting Points with Worst Slack</a>
********************************

                  Starting                                               Arrival           
Instance          Reference           Type        Pin     Net            Time        Slack 
                  Clock                                                                    
-------------------------------------------------------------------------------------------
u2.counter[0]     prox_detect|clk     FD1S3AX     Q       counter[0]     1.044       -0.379
u2.counter[1]     prox_detect|clk     FD1S3AX     Q       counter[1]     1.044       -0.236
u2.counter[2]     prox_detect|clk     FD1S3AX     Q       counter[2]     1.044       -0.236
u4.cnt[0]         prox_detect|clk     FD1S3AX     Q       cnt[0]         1.044       -0.094
u2.counter[3]     prox_detect|clk     FD1S3AX     Q       counter[3]     1.044       -0.094
u2.counter[4]     prox_detect|clk     FD1S3AX     Q       counter[4]     1.044       -0.094
u4.cnt[1]         prox_detect|clk     FD1S3AX     Q       cnt[1]         1.108       -0.015
u4.cnt[2]         prox_detect|clk     FD1S3AX     Q       cnt[2]         1.108       -0.015
u2.counter[5]     prox_detect|clk     FD1S3AX     Q       counter[5]     1.044       0.049 
u2.counter[6]     prox_detect|clk     FD1S3AX     Q       counter[6]     1.044       0.049 
===========================================================================================


<a name=endingSlack33></a>Ending Points with Worst Slack</a>
******************************

                   Starting                                                      Required           
Instance           Reference           Type        Pin     Net                   Time         Slack 
                   Clock                                                                            
----------------------------------------------------------------------------------------------------
u2.counter[12]     prox_detect|clk     FD1S3AX     D       counter_3[12]         5.089        -0.379
u2.counter[15]     prox_detect|clk     FD1S3AX     D       un5_counter_1[15]     4.894        -0.242
u2.counter[9]      prox_detect|clk     FD1S3AX     D       counter_3[9]          5.089        -0.236
u2.counter[10]     prox_detect|clk     FD1S3AX     D       counter_3[10]         5.089        -0.236
u2.counter[13]     prox_detect|clk     FD1S3AX     D       un5_counter_1[13]     4.894        -0.100
u2.counter[14]     prox_detect|clk     FD1S3AX     D       un5_counter_1[14]     4.894        -0.100
u4.cnt[7]          prox_detect|clk     FD1S3AX     D       cnt_lm[7]             5.089        -0.094
u4.cnt[8]          prox_detect|clk     FD1S3AX     D       cnt_lm[8]             5.089        -0.094
u2.counter[8]      prox_detect|clk     FD1S3AX     D       counter_3[8]          5.089        -0.094
u2.counter[11]     prox_detect|clk     FD1S3AX     D       un5_counter_1[11]     4.894        0.043 
====================================================================================================



<a name=worstPaths34></a>Worst Path Information</a>
<a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\impl1\prox_detect_impl1.srr:srsfD:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\impl1\prox_detect_impl1.srs:fp:102142:104680:@XP_NAMES_GATE">View Worst Path in Analyst</a>
***********************


Path information for path number 1: 
      Requested Period:                      5.000
    - Setup time:                            -0.089
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.089

    - Propagation time:                      5.468
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.379

    Number of logic level(s):                8
    Starting point:                          u2.counter[0] / Q
    Ending point:                            u2.counter[12] / D
    The start point is clocked by            prox_detect|clk [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK
    The end   point is clocked by            prox_detect|clk [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK

Instance / Net                             Pin      Pin               Arrival     No. of    
Name                          Type         Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------
u2.counter[0]                 FD1S3AX      Q        Out     1.044     1.044 r     -         
counter[0]                    Net          -        -       -         -           2         
u2.un5_counter_1_cry_0_0      CCU2D        A1       In      0.000     1.044 r     -         
u2.un5_counter_1_cry_0_0      CCU2D        COUT     Out     1.544     2.588 r     -         
un5_counter_1_cry_0           Net          -        -       -         -           1         
u2.un5_counter_1_cry_1_0      CCU2D        CIN      In      0.000     2.588 r     -         
u2.un5_counter_1_cry_1_0      CCU2D        COUT     Out     0.143     2.731 r     -         
un5_counter_1_cry_2           Net          -        -       -         -           1         
u2.un5_counter_1_cry_3_0      CCU2D        CIN      In      0.000     2.731 r     -         
u2.un5_counter_1_cry_3_0      CCU2D        COUT     Out     0.143     2.874 r     -         
un5_counter_1_cry_4           Net          -        -       -         -           1         
u2.un5_counter_1_cry_5_0      CCU2D        CIN      In      0.000     2.874 r     -         
u2.un5_counter_1_cry_5_0      CCU2D        COUT     Out     0.143     3.017 r     -         
un5_counter_1_cry_6           Net          -        -       -         -           1         
u2.un5_counter_1_cry_7_0      CCU2D        CIN      In      0.000     3.017 r     -         
u2.un5_counter_1_cry_7_0      CCU2D        COUT     Out     0.143     3.159 r     -         
un5_counter_1_cry_8           Net          -        -       -         -           1         
u2.un5_counter_1_cry_9_0      CCU2D        CIN      In      0.000     3.159 r     -         
u2.un5_counter_1_cry_9_0      CCU2D        COUT     Out     0.143     3.302 r     -         
un5_counter_1_cry_10          Net          -        -       -         -           1         
u2.un5_counter_1_cry_11_0     CCU2D        CIN      In      0.000     3.302 r     -         
u2.un5_counter_1_cry_11_0     CCU2D        S1       Out     1.549     4.851 r     -         
un5_counter_1_cry_11_0_S1     Net          -        -       -         -           1         
u2.counter_3[12]              ORCALUT4     A        In      0.000     4.851 r     -         
u2.counter_3[12]              ORCALUT4     Z        Out     0.617     5.468 r     -         
counter_3[12]                 Net          -        -       -         -           1         
u2.counter[12]                FD1S3AX      D        In      0.000     5.468 r     -         
============================================================================================


Path information for path number 2: 
      Requested Period:                      5.000
    - Setup time:                            0.106
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.894

    - Propagation time:                      5.137
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.242

    Number of logic level(s):                9
    Starting point:                          u2.counter[0] / Q
    Ending point:                            u2.counter[15] / D
    The start point is clocked by            prox_detect|clk [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK
    The end   point is clocked by            prox_detect|clk [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK

Instance / Net                            Pin      Pin               Arrival     No. of    
Name                          Type        Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------
u2.counter[0]                 FD1S3AX     Q        Out     1.044     1.044 r     -         
counter[0]                    Net         -        -       -         -           2         
u2.un5_counter_1_cry_0_0      CCU2D       A1       In      0.000     1.044 r     -         
u2.un5_counter_1_cry_0_0      CCU2D       COUT     Out     1.544     2.588 r     -         
un5_counter_1_cry_0           Net         -        -       -         -           1         
u2.un5_counter_1_cry_1_0      CCU2D       CIN      In      0.000     2.588 r     -         
u2.un5_counter_1_cry_1_0      CCU2D       COUT     Out     0.143     2.731 r     -         
un5_counter_1_cry_2           Net         -        -       -         -           1         
u2.un5_counter_1_cry_3_0      CCU2D       CIN      In      0.000     2.731 r     -         
u2.un5_counter_1_cry_3_0      CCU2D       COUT     Out     0.143     2.874 r     -         
un5_counter_1_cry_4           Net         -        -       -         -           1         
u2.un5_counter_1_cry_5_0      CCU2D       CIN      In      0.000     2.874 r     -         
u2.un5_counter_1_cry_5_0      CCU2D       COUT     Out     0.143     3.017 r     -         
un5_counter_1_cry_6           Net         -        -       -         -           1         
u2.un5_counter_1_cry_7_0      CCU2D       CIN      In      0.000     3.017 r     -         
u2.un5_counter_1_cry_7_0      CCU2D       COUT     Out     0.143     3.159 r     -         
un5_counter_1_cry_8           Net         -        -       -         -           1         
u2.un5_counter_1_cry_9_0      CCU2D       CIN      In      0.000     3.159 r     -         
u2.un5_counter_1_cry_9_0      CCU2D       COUT     Out     0.143     3.302 r     -         
un5_counter_1_cry_10          Net         -        -       -         -           1         
u2.un5_counter_1_cry_11_0     CCU2D       CIN      In      0.000     3.302 r     -         
u2.un5_counter_1_cry_11_0     CCU2D       COUT     Out     0.143     3.445 r     -         
un5_counter_1_cry_12          Net         -        -       -         -           1         
u2.un5_counter_1_cry_13_0     CCU2D       CIN      In      0.000     3.445 r     -         
u2.un5_counter_1_cry_13_0     CCU2D       COUT     Out     0.143     3.588 r     -         
un5_counter_1_cry_14          Net         -        -       -         -           1         
u2.un5_counter_1_s_15_0       CCU2D       CIN      In      0.000     3.588 r     -         
u2.un5_counter_1_s_15_0       CCU2D       S0       Out     1.549     5.137 r     -         
un5_counter_1[15]             Net         -        -       -         -           1         
u2.counter[15]                FD1S3AX     D        In      0.000     5.137 r     -         
===========================================================================================


Path information for path number 3: 
      Requested Period:                      5.000
    - Setup time:                            -0.089
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.089

    - Propagation time:                      5.325
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.237

    Number of logic level(s):                7
    Starting point:                          u2.counter[1] / Q
    Ending point:                            u2.counter[12] / D
    The start point is clocked by            prox_detect|clk [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK
    The end   point is clocked by            prox_detect|clk [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK

Instance / Net                             Pin      Pin               Arrival     No. of    
Name                          Type         Name     Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------
u2.counter[1]                 FD1S3AX      Q        Out     1.044     1.044 r     -         
counter[1]                    Net          -        -       -         -           2         
u2.un5_counter_1_cry_1_0      CCU2D        A0       In      0.000     1.044 r     -         
u2.un5_counter_1_cry_1_0      CCU2D        COUT     Out     1.544     2.588 r     -         
un5_counter_1_cry_2           Net          -        -       -         -           1         
u2.un5_counter_1_cry_3_0      CCU2D        CIN      In      0.000     2.588 r     -         
u2.un5_counter_1_cry_3_0      CCU2D        COUT     Out     0.143     2.731 r     -         
un5_counter_1_cry_4           Net          -        -       -         -           1         
u2.un5_counter_1_cry_5_0      CCU2D        CIN      In      0.000     2.731 r     -         
u2.un5_counter_1_cry_5_0      CCU2D        COUT     Out     0.143     2.874 r     -         
un5_counter_1_cry_6           Net          -        -       -         -           1         
u2.un5_counter_1_cry_7_0      CCU2D        CIN      In      0.000     2.874 r     -         
u2.un5_counter_1_cry_7_0      CCU2D        COUT     Out     0.143     3.017 r     -         
un5_counter_1_cry_8           Net          -        -       -         -           1         
u2.un5_counter_1_cry_9_0      CCU2D        CIN      In      0.000     3.017 r     -         
u2.un5_counter_1_cry_9_0      CCU2D        COUT     Out     0.143     3.159 r     -         
un5_counter_1_cry_10          Net          -        -       -         -           1         
u2.un5_counter_1_cry_11_0     CCU2D        CIN      In      0.000     3.159 r     -         
u2.un5_counter_1_cry_11_0     CCU2D        S1       Out     1.549     4.708 r     -         
un5_counter_1_cry_11_0_S1     Net          -        -       -         -           1         
u2.counter_3[12]              ORCALUT4     A        In      0.000     4.708 r     -         
u2.counter_3[12]              ORCALUT4     Z        Out     0.617     5.325 r     -         
counter_3[12]                 Net          -        -       -         -           1         
u2.counter[12]                FD1S3AX      D        In      0.000     5.325 r     -         
============================================================================================




====================================
<a name=clockReport35></a>Detailed Report for Clock: rpr0521rs_driver|clk_400khz_derived_clock</a>
====================================



<a name=startingSlack36></a>Starting Points with Worst Slack</a>
********************************

                       Starting                                                                              Arrival            
Instance               Reference                                     Type        Pin     Net                 Time        Slack  
                       Clock                                                                                                    
--------------------------------------------------------------------------------------------------------------------------------
u1.ch1_dat[7]          rpr0521rs_driver|clk_400khz_derived_clock     FD1P3AX     Q       ch1_dat[7]          1.256       -62.936
u1.ch1_dat_fast[5]     rpr0521rs_driver|clk_400khz_derived_clock     FD1P3AX     Q       ch1_dat_fast[5]     1.108       -62.931
u1.ch1_dat[2]          rpr0521rs_driver|clk_400khz_derived_clock     FD1P3AX     Q       ch1_dat[2]          1.244       -62.924
u1.ch1_dat[1]          rpr0521rs_driver|clk_400khz_derived_clock     FD1P3AX     Q       ch1_dat[1]          1.236       -62.916
u1.ch0_dat_0_rep2      rpr0521rs_driver|clk_400khz_derived_clock     FD1P3AX     Q       ch0_dat_0_rep2      1.228       -62.908
u1.ch0_dat_2_rep1      rpr0521rs_driver|clk_400khz_derived_clock     FD1P3AX     Q       ch0_dat_2_rep1      1.204       -62.884
u1.ch0_dat_fast[0]     rpr0521rs_driver|clk_400khz_derived_clock     FD1P3AX     Q       ch0_dat_fast[0]     1.108       -62.870
u1.ch1_dat_fast[0]     rpr0521rs_driver|clk_400khz_derived_clock     FD1P3AX     Q       ch1_dat_fast[0]     1.044       -62.867
u1.ch0_dat_fast[1]     rpr0521rs_driver|clk_400khz_derived_clock     FD1P3AX     Q       ch0_dat_fast[1]     1.148       -62.836
u1.ch0_dat_fast[2]     rpr0521rs_driver|clk_400khz_derived_clock     FD1P3AX     Q       ch0_dat_fast[2]     1.148       -62.836
================================================================================================================================


<a name=endingSlack37></a>Ending Points with Worst Slack</a>
******************************

                     Starting                                                                              Required            
Instance             Reference                                     Type        Pin     Net                 Time         Slack  
                     Clock                                                                                                     
-------------------------------------------------------------------------------------------------------------------------------
u4.data[9]           rpr0521rs_driver|clk_400khz_derived_clock     FD1P3AX     D       data_12[9]          5.462        -62.936
u4.data[8]           rpr0521rs_driver|clk_400khz_derived_clock     FD1P3AX     D       data_12[8]          5.089        -61.696
u4.data[10]          rpr0521rs_driver|clk_400khz_derived_clock     FD1P3AX     D       data_12[10]         5.089        -61.696
u4.data[12]          rpr0521rs_driver|clk_400khz_derived_clock     FD1P3AX     D       data_12[12]         5.089        -61.679
u4.data[13]          rpr0521rs_driver|clk_400khz_derived_clock     FD1P3AX     D       data_12[13]         5.089        -61.086
u4.data[11]          rpr0521rs_driver|clk_400khz_derived_clock     FD1P3AX     D       data_12[11]         5.462        -60.940
u4.data[14]          rpr0521rs_driver|clk_400khz_derived_clock     FD1P3AX     D       data_12[14]         5.462        -60.329
u1.cnt_delay[23]     rpr0521rs_driver|clk_400khz_derived_clock     FD1P3AX     D       cnt_delay_s[23]     9.894        -1.570 
u1.cnt_delay[21]     rpr0521rs_driver|clk_400khz_derived_clock     FD1P3AX     D       cnt_delay_s[21]     9.894        -1.427 
u1.cnt_delay[22]     rpr0521rs_driver|clk_400khz_derived_clock     FD1P3AX     D       cnt_delay_s[22]     9.894        -1.427 
===============================================================================================================================



<a name=worstPaths38></a>Worst Path Information</a>
<a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\impl1\prox_detect_impl1.srr:srsfD:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\impl1\prox_detect_impl1.srs:fp:117721:140773:@XP_NAMES_GATE">View Worst Path in Analyst</a>
***********************


Path information for path number 1: 
      Requested Period:                      5.000
    - Setup time:                            -0.462
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.462

    - Propagation time:                      68.399
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -62.936

    Number of logic level(s):                67
    Starting point:                          u1.ch1_dat[7] / Q
    Ending point:                            u4.data[9] / D
    The start point is clocked by            rpr0521rs_driver|clk_400khz_derived_clock [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK
    The end   point is clocked by            segment_scan|clk_40khz_derived_clock [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK

Instance / Net                                               Pin      Pin               Arrival      No. of    
Name                                            Type         Name     Dir     Delay     Time         Fan Out(s)
---------------------------------------------------------------------------------------------------------------
u1.ch1_dat[7]                                   FD1P3AX      Q        Out     1.256     1.256 r      -         
ch1_dat[7]                                      Net          -        -       -         -            14        
u2.un1_ch1_dat_1_cry_6_0                        CCU2D        A1       In      0.000     1.256 r      -         
u2.un1_ch1_dat_1_cry_6_0                        CCU2D        COUT     Out     1.544     2.800 r      -         
un1_ch1_dat_1_cry_7                             Net          -        -       -         -            1         
u2.un1_ch1_dat_1_cry_8_0                        CCU2D        CIN      In      0.000     2.800 r      -         
u2.un1_ch1_dat_1_cry_8_0                        CCU2D        S0       Out     1.685     4.485 r      -         
un1_ch1_dat_1[8]                                Net          -        -       -         -            3         
u2.un1_lux_1_d1_39                              ORCALUT4     B        In      0.000     4.485 r      -         
u2.un1_lux_1_d1_39                              ORCALUT4     Z        Out     1.017     5.502 r      -         
un1_lux_1_d1_39                                 Net          -        -       -         -            1         
u2.un1_lux_1_s0_m1_0_cry_7_0                    CCU2D        C1       In      0.000     5.502 r      -         
u2.un1_lux_1_s0_m1_0_cry_7_0                    CCU2D        COUT     Out     1.544     7.047 r      -         
un1_lux_1_s0_m1_0_cry_8                         Net          -        -       -         -            1         
u2.un1_lux_1_s0_m1_0_cry_9_0                    CCU2D        CIN      In      0.000     7.047 r      -         
u2.un1_lux_1_s0_m1_0_cry_9_0                    CCU2D        COUT     Out     0.143     7.189 r      -         
un1_lux_1_s0_m1_0_cry_10                        Net          -        -       -         -            1         
u2.un1_lux_1_s0_m1_0_cry_11_0                   CCU2D        CIN      In      0.000     7.189 r      -         
u2.un1_lux_1_s0_m1_0_cry_11_0                   CCU2D        COUT     Out     0.143     7.332 r      -         
un1_lux_1_s0_m1_0_cry_12                        Net          -        -       -         -            1         
u2.un1_lux_1_s0_m1_0_cry_13_0                   CCU2D        CIN      In      0.000     7.332 r      -         
u2.un1_lux_1_s0_m1_0_cry_13_0                   CCU2D        COUT     Out     0.143     7.475 r      -         
un1_lux_1_s0_m1_0_cry_14                        Net          -        -       -         -            1         
u2.un1_lux_1_s0_m1_0_cry_15_0                   CCU2D        CIN      In      0.000     7.475 r      -         
u2.un1_lux_1_s0_m1_0_cry_15_0                   CCU2D        COUT     Out     0.143     7.618 r      -         
un1_lux_1_s0_m1_0_cry_16                        Net          -        -       -         -            1         
u2.un1_lux_1_s0_m1_0_cry_17_0                   CCU2D        CIN      In      0.000     7.618 r      -         
u2.un1_lux_1_s0_m1_0_cry_17_0                   CCU2D        COUT     Out     0.143     7.761 r      -         
un1_lux_1_s0_m1_0_cry_18                        Net          -        -       -         -            1         
u2.un1_lux_1_s0_m1_0_cry_19_0                   CCU2D        CIN      In      0.000     7.761 r      -         
u2.un1_lux_1_s0_m1_0_cry_19_0                   CCU2D        COUT     Out     0.143     7.903 r      -         
un1_lux_1_s0_m1_0_cry_20                        Net          -        -       -         -            1         
u2.un1_lux_1_s0_m1_0_cry_21_0                   CCU2D        CIN      In      0.000     7.903 r      -         
u2.un1_lux_1_s0_m1_0_cry_21_0                   CCU2D        COUT     Out     0.143     8.046 r      -         
un1_lux_1_s0_m1_0_cry_22                        Net          -        -       -         -            1         
u2.un1_lux_1_s0_m1_0_cry_23_0                   CCU2D        CIN      In      0.000     8.046 r      -         
u2.un1_lux_1_s0_m1_0_cry_23_0                   CCU2D        COUT     Out     0.143     8.189 r      -         
un1_lux_1_s0_m1_0_cry_24                        Net          -        -       -         -            1         
u2.un1_lux_1_s0_m1_0_cry_25_0                   CCU2D        CIN      In      0.000     8.189 r      -         
u2.un1_lux_1_s0_m1_0_cry_25_0                   CCU2D        S0       Out     1.549     9.738 r      -         
un1_lux_1_s0_m1_0_cry_25_0_S0                   Net          -        -       -         -            1         
u2.un1_lux_1_s0_m1[27]                          ORCALUT4     A        In      0.000     9.738 r      -         
u2.un1_lux_1_s0_m1[27]                          ORCALUT4     Z        Out     1.017     10.755 r     -         
un1_lux_1_s0_m1[27]                             Net          -        -       -         -            1         
u2.un1_lux_1_s0_d[27]                           ORCALUT4     C        In      0.000     10.755 r     -         
u2.un1_lux_1_s0_d[27]                           ORCALUT4     Z        Out     1.193     11.948 r     -         
un1_lux_1_s0_d[27]                              Net          -        -       -         -            4         
u2.u1.CO2_0_0_mb_mb_1_0                         ORCALUT4     B        In      0.000     11.948 r     -         
u2.u1.CO2_0_0_mb_mb_1_0                         ORCALUT4     Z        Out     1.017     12.964 f     -         
shift_m1_e_1_1_0                                Net          -        -       -         -            1         
u2.u1.CO2_0_0_mb_mb                             ORCALUT4     A        In      0.000     12.964 f     -         
u2.u1.CO2_0_0_mb_mb                             ORCALUT4     Z        Out     1.089     14.053 r     -         
CO2_0_0                                         Net          -        -       -         -            2         
u2.u1.CO2_2_0                                   ORCALUT4     A        In      0.000     14.053 r     -         
u2.u1.CO2_2_0                                   ORCALUT4     Z        Out     1.089     15.142 r     -         
CO2_2_0                                         Net          -        -       -         -            2         
u2.u1.shift_reg_54_i_o3[37]                     ORCALUT4     B        In      0.000     15.142 r     -         
u2.u1.shift_reg_54_i_o3[37]                     ORCALUT4     Z        Out     1.225     16.367 r     -         
CO0_118                                         Net          -        -       -         -            5         
u2.u1.shift_reg_41[34]                          ORCALUT4     C        In      0.000     16.367 r     -         
u2.u1.shift_reg_41[34]                          ORCALUT4     Z        Out     1.277     17.644 r     -         
shift_reg_41[34]                                Net          -        -       -         -            10        
u2.u1.shift_reg_41_i_i_a2_RNIKQ44[32]           ORCALUT4     C        In      0.000     17.644 r     -         
u2.u1.shift_reg_41_i_i_a2_RNIKQ44[32]           ORCALUT4     Z        Out     1.017     18.660 r     -         
shift_reg_41_i_i_a2_RNIKQ44[32]                 Net          -        -       -         -            1         
u2.u1.shift_reg_41_i_i_a2_RNI7T8O[32]           ORCALUT4     D        In      0.000     18.660 r     -         
u2.u1.shift_reg_41_i_i_a2_RNI7T8O[32]           ORCALUT4     Z        Out     1.277     19.937 f     -         
CO2_108                                         Net          -        -       -         -            10        
u2.u1.shift_reg_51_RNIOB4OA[34]                 ORCALUT4     B        In      0.000     19.937 f     -         
u2.u1.shift_reg_51_RNIOB4OA[34]                 ORCALUT4     Z        Out     1.225     21.162 r     -         
CO1_112_fc                                      Net          -        -       -         -            5         
u2.u1.shift_reg_51_RNIE8KV51[34]                ORCALUT4     B        In      0.000     21.162 r     -         
u2.u1.shift_reg_51_RNIE8KV51[34]                ORCALUT4     Z        Out     1.089     22.251 r     -         
shift_reg_51_RNIE8KV51[34]                      Net          -        -       -         -            2         
u2.u1.shift_reg_61_RNI73H881[33]                ORCALUT4     A        In      0.000     22.251 r     -         
u2.u1.shift_reg_61_RNI73H881[33]                ORCALUT4     Z        Out     1.233     23.484 f     -         
CO1_108                                         Net          -        -       -         -            6         
u2.u1.shift_reg_87_N_2L1_1                      ORCALUT4     B        In      0.000     23.484 f     -         
u2.u1.shift_reg_87_N_2L1_1                      ORCALUT4     Z        Out     1.017     24.500 r     -         
shift_reg_87_N_2L1_1                            Net          -        -       -         -            1         
u2.u1.shift_reg_87[38]                          ORCALUT4     C        In      0.000     24.500 r     -         
u2.u1.shift_reg_87[38]                          ORCALUT4     Z        Out     1.193     25.693 r     -         
shift_reg_87[38]                                Net          -        -       -         -            4         
u2.u1.shift_reg_100[38]                         ORCALUT4     C        In      0.000     25.693 r     -         
u2.u1.shift_reg_100[38]                         ORCALUT4     Z        Out     1.193     26.886 r     -         
shift_reg_100[38]                               Net          -        -       -         -            4         
u2.u1.shift_reg_113_0_a2_0_a2[37]               ORCALUT4     C        In      0.000     26.886 r     -         
u2.u1.shift_reg_113_0_a2_0_a2[37]               ORCALUT4     Z        Out     1.233     28.119 r     -         
N_694                                           Net          -        -       -         -            6         
u2.u1.shift_reg_113_RNIEE992[38]                ORCALUT4     B        In      0.000     28.119 r     -         
u2.u1.shift_reg_113_RNIEE992[38]                ORCALUT4     Z        Out     1.017     29.136 r     -         
shift_reg_113_RNIEE992[38]                      Net          -        -       -         -            1         
u2.u1.shift_reg_113_RNINRTK3[39]                ORCALUT4     A        In      0.000     29.136 r     -         
u2.u1.shift_reg_113_RNINRTK3[39]                ORCALUT4     Z        Out     1.153     30.288 r     -         
CO1_90                                          Net          -        -       -         -            3         
u2.u1.shift_reg_113_0_a2_0_a2_RNIKPG78[37]      ORCALUT4     C        In      0.000     30.288 r     -         
u2.u1.shift_reg_113_0_a2_0_a2_RNIKPG78[37]      ORCALUT4     Z        Out     1.265     31.553 r     -         
CO2_85                                          Net          -        -       -         -            8         
u2.u1.shift_reg_145_N_2L1_0_RNIPU5A9            ORCALUT4     A        In      0.000     31.553 r     -         
u2.u1.shift_reg_145_N_2L1_0_RNIPU5A9            ORCALUT4     Z        Out     1.017     32.570 r     -         
shift_reg_145_N_2L1_0_RNIPU5A9                  Net          -        -       -         -            1         
u2.u1.shift_reg_145_i_i_a2_0_RNIDFJ8J[37]       ORCALUT4     B        In      0.000     32.570 r     -         
u2.u1.shift_reg_145_i_i_a2_0_RNIDFJ8J[37]       ORCALUT4     Z        Out     1.225     33.795 r     -         
CO2_80                                          Net          -        -       -         -            5         
u2.u1.shift_reg_161[38]                         ORCALUT4     B        In      0.000     33.795 r     -         
u2.u1.shift_reg_161[38]                         ORCALUT4     Z        Out     1.233     35.028 r     -         
shift_reg_161[38]                               Net          -        -       -         -            6         
u2.u1.shift_reg_161_RNI4KREM[38]                ORCALUT4     B        In      0.000     35.028 r     -         
u2.u1.shift_reg_161_RNI4KREM[38]                ORCALUT4     Z        Out     1.249     36.276 r     -         
CO0_74                                          Net          -        -       -         -            7         
u2.u1.shift_reg_161_0_a2_0_a2_RNICBNDN[37]      ORCALUT4     B        In      0.000     36.276 r     -         
u2.u1.shift_reg_161_0_a2_0_a2_RNICBNDN[37]      ORCALUT4     Z        Out     1.017     37.293 r     -         
CO1_67_1                                        Net          -        -       -         -            1         
u2.u1.shift_reg_199_i_i_a2_0_RNIC00HF1[37]      ORCALUT4     B        In      0.000     37.293 r     -         
u2.u1.shift_reg_199_i_i_a2_0_RNIC00HF1[37]      ORCALUT4     Z        Out     1.233     38.526 r     -         
CO1_67                                          Net          -        -       -         -            6         
u2.u1.shift_reg_180_0_a2_0_a2_RNIQ1HB72[37]     ORCALUT4     D        In      0.000     38.526 r     -         
u2.u1.shift_reg_180_0_a2_0_a2_RNIQ1HB72[37]     ORCALUT4     Z        Out     1.281     39.807 r     -         
CO2_63                                          Net          -        -       -         -            11        
u2.u1.shift_reg_180_RNINETUU2[38]               ORCALUT4     B        In      0.000     39.807 r     -         
u2.u1.shift_reg_180_RNINETUU2[38]               ORCALUT4     Z        Out     1.281     41.088 r     -         
CO0_62                                          Net          -        -       -         -            11        
u2.u1.shift_reg_240_i_i_a2_0[37]                ORCALUT4     B        In      0.000     41.088 r     -         
u2.u1.shift_reg_240_i_i_a2_0[37]                ORCALUT4     Z        Out     1.153     42.240 r     -         
shift_reg_240_i_i_a2_0[37]                      Net          -        -       -         -            3         
u2.u1.shift_reg_240_i_i_a2_0_RNI4FR695[37]      ORCALUT4     C        In      0.000     42.240 r     -         
u2.u1.shift_reg_240_i_i_a2_0_RNI4FR695[37]      ORCALUT4     Z        Out     1.193     43.433 r     -         
CO1_53                                          Net          -        -       -         -            4         
u2.u1.shift_reg_218_RNILMTP0O_0[38]             ORCALUT4     A        In      0.000     43.433 r     -         
u2.u1.shift_reg_218_RNILMTP0O_0[38]             ORCALUT4     Z        Out     1.273     44.706 r     -         
CO0_48                                          Net          -        -       -         -            9         
u2.u1.shift_reg_262[38]                         ORCALUT4     A        In      0.000     44.706 r     -         
u2.u1.shift_reg_262[38]                         ORCALUT4     Z        Out     1.265     45.971 r     -         
shift_reg_262[38]                               Net          -        -       -         -            8         
u2.u1.shift_reg_262_RNI4H628H[38]               ORCALUT4     C        In      0.000     45.971 r     -         
u2.u1.shift_reg_262_RNI4H628H[38]               ORCALUT4     Z        Out     1.153     47.124 r     -         
CO2_42                                          Net          -        -       -         -            3         
u2.u1.shift_reg_287_i_0_RNIHGFSIE1_0[41]        ORCALUT4     C        In      0.000     47.124 r     -         
u2.u1.shift_reg_287_i_0_RNIHGFSIE1_0[41]        ORCALUT4     Z        Out     1.017     48.140 r     -         
shift_reg_287_i_0_RNIHGFSIE1_0[41]              Net          -        -       -         -            1         
u2.u1.shift_reg_265_i_i_a2_RNIMA80LU2[41]       ORCALUT4     D        In      0.000     48.140 r     -         
u2.u1.shift_reg_265_i_i_a2_RNIMA80LU2[41]       ORCALUT4     Z        Out     1.017     49.157 f     -         
shift_reg_265_i_i_a2_RNIMA80LU2[41]             Net          -        -       -         -            1         
u2.u1.shift_reg_265_RNIV34TQE1[42]              ORCALUT4     C        In      0.000     49.157 f     -         
u2.u1.shift_reg_265_RNIV34TQE1[42]              ORCALUT4     Z        Out     1.305     50.462 r     -         
CO0_35                                          Net          -        -       -         -            15        
u2.u1.shift_reg_312[42]                         ORCALUT4     B        In      0.000     50.462 r     -         
u2.u1.shift_reg_312[42]                         ORCALUT4     Z        Out     1.249     51.711 r     -         
shift_reg_312[42]                               Net          -        -       -         -            7         
u2.u1.shift_reg_312_RNITFN4GL3[43]              ORCALUT4     C        In      0.000     51.711 r     -         
u2.u1.shift_reg_312_RNITFN4GL3[43]              ORCALUT4     Z        Out     1.273     52.984 r     -         
un1_shift_reg_axb0_0                            Net          -        -       -         -            9         
u2.u1._l27\.un1_shift_reg_c3_0_am               ORCALUT4     B        In      0.000     52.984 r     -         
u2.u1._l27\.un1_shift_reg_c3_0_am               ORCALUT4     Z        Out     1.017     54.000 f     -         
un1_shift_reg_c3_0_am                           Net          -        -       -         -            1         
u2.u1._l27\.un1_shift_reg_c3_0                  PFUMX        BLUT     In      0.000     54.000 f     -         
u2.u1._l27\.un1_shift_reg_c3_0                  PFUMX        Z        Out     0.470     54.471 f     -         
un1_shift_reg_0                                 Net          -        -       -         -            9         
u2.u1._l27\.shift_reg_365_axbxc2_0_bm           ORCALUT4     D        In      0.000     54.471 f     -         
u2.u1._l27\.shift_reg_365_axbxc2_0_bm           ORCALUT4     Z        Out     1.017     55.487 r     -         
shift_reg_365_axbxc2_0_bm                       Net          -        -       -         -            1         
u2.u1._l27\.shift_reg_365_axbxc2_0              PFUMX        ALUT     In      0.000     55.487 r     -         
u2.u1._l27\.shift_reg_365_axbxc2_0              PFUMX        Z        Out     0.422     55.910 r     -         
shift_reg_365[47]                               Net          -        -       -         -            5         
u2.u1._l28\.shift_reg_393_axbxc1_N_2L1          ORCALUT4     A        In      0.000     55.910 r     -         
u2.u1._l28\.shift_reg_393_axbxc1_N_2L1          ORCALUT4     Z        Out     1.017     56.926 f     -         
shift_reg_393_axbxc1_N_2L1                      Net          -        -       -         -            1         
u2.u1._l28\.shift_reg_393_axbxc1                ORCALUT4     C        In      0.000     56.926 f     -         
u2.u1._l28\.shift_reg_393_axbxc1                ORCALUT4     Z        Out     1.273     58.199 r     -         
shift_reg_393[46]                               Net          -        -       -         -            9         
u2.u1._l29\.shift_reg_421_axbxc1_1              ORCALUT4     A        In      0.000     58.199 r     -         
u2.u1._l29\.shift_reg_421_axbxc1_1              ORCALUT4     Z        Out     1.017     59.216 f     -         
_m2_7_1                                         Net          -        -       -         -            1         
u2.u1._l29\.shift_reg_421_axbxc1                ORCALUT4     D        In      0.000     59.216 f     -         
u2.u1._l29\.shift_reg_421_axbxc1                ORCALUT4     Z        Out     1.265     60.481 r     -         
shift_reg_421[46]                               Net          -        -       -         -            8         
u2.u1._l30\.un1_shift_reg_3_ac0_5               ORCALUT4     B        In      0.000     60.481 r     -         
u2.u1._l30\.un1_shift_reg_3_ac0_5               ORCALUT4     Z        Out     1.089     61.570 f     -         
un1_shift_reg_3                                 Net          -        -       -         -            2         
u2.u1._l30\.shift_reg_449_axbxc2                ORCALUT4     D        In      0.000     61.570 f     -         
u2.u1._l30\.shift_reg_449_axbxc2                ORCALUT4     Z        Out     1.017     62.586 r     -         
shift_reg_449[47]                               Net          -        -       -         -            1         
u2.u1._l30\.shift_reg_449_axbxc2_RNI5P8VIA      ORCALUT4     C        In      0.000     62.586 r     -         
u2.u1._l30\.shift_reg_449_axbxc2_RNI5P8VIA      ORCALUT4     Z        Out     1.317     63.903 r     -         
shift_reg_477[47]                               Net          -        -       -         -            18        
u4.data_6_14_8_.m8                              ORCALUT4     A        In      0.000     63.903 r     -         
u4.data_6_14_8_.m8                              ORCALUT4     Z        Out     1.017     64.920 r     -         
N_9_0                                           Net          -        -       -         -            1         
u4.data_12_1_d[9]                               ORCALUT4     D        In      0.000     64.920 r     -         
u4.data_12_1_d[9]                               ORCALUT4     Z        Out     1.017     65.937 f     -         
data_12_1_d[9]                                  Net          -        -       -         -            1         
u4.data_12_3_d_d_0[9]                           PFUMX        BLUT     In      0.000     65.937 f     -         
u4.data_12_3_d_d_0[9]                           PFUMX        Z        Out     0.214     66.151 f     -         
data_12_3_d_d_0[9]                              Net          -        -       -         -            1         
u4.data_12_3_d[9]                               ORCALUT4     A        In      0.000     66.151 f     -         
u4.data_12_3_d[9]                               ORCALUT4     Z        Out     1.017     67.168 f     -         
data_12_3_d[9]                                  Net          -        -       -         -            1         
u4.data_12_7_am[9]                              ORCALUT4     B        In      0.000     67.168 f     -         
u4.data_12_7_am[9]                              ORCALUT4     Z        Out     1.017     68.185 f     -         
data_12_7_am[9]                                 Net          -        -       -         -            1         
u4.data_12_7[9]                                 PFUMX        BLUT     In      0.000     68.185 f     -         
u4.data_12_7[9]                                 PFUMX        Z        Out     0.214     68.399 f     -         
data_12[9]                                      Net          -        -       -         -            1         
u4.data[9]                                      FD1P3AX      D        In      0.000     68.399 f     -         
===============================================================================================================


Path information for path number 2: 
      Requested Period:                      5.000
    - Setup time:                            -0.462
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.462

    - Propagation time:                      68.399
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -62.936

    Number of logic level(s):                67
    Starting point:                          u1.ch1_dat[7] / Q
    Ending point:                            u4.data[9] / D
    The start point is clocked by            rpr0521rs_driver|clk_400khz_derived_clock [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK
    The end   point is clocked by            segment_scan|clk_40khz_derived_clock [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK

Instance / Net                                               Pin      Pin               Arrival      No. of    
Name                                            Type         Name     Dir     Delay     Time         Fan Out(s)
---------------------------------------------------------------------------------------------------------------
u1.ch1_dat[7]                                   FD1P3AX      Q        Out     1.256     1.256 r      -         
ch1_dat[7]                                      Net          -        -       -         -            14        
u2.un1_ch1_dat_1_cry_6_0                        CCU2D        A1       In      0.000     1.256 r      -         
u2.un1_ch1_dat_1_cry_6_0                        CCU2D        COUT     Out     1.544     2.800 r      -         
un1_ch1_dat_1_cry_7                             Net          -        -       -         -            1         
u2.un1_ch1_dat_1_cry_8_0                        CCU2D        CIN      In      0.000     2.800 r      -         
u2.un1_ch1_dat_1_cry_8_0                        CCU2D        COUT     Out     0.143     2.943 r      -         
un1_ch1_dat_1_cry_9                             Net          -        -       -         -            1         
u2.un1_ch1_dat_1_cry_10_0                       CCU2D        CIN      In      0.000     2.943 r      -         
u2.un1_ch1_dat_1_cry_10_0                       CCU2D        S0       Out     1.685     4.628 r      -         
un1_ch1_dat_1[10]                               Net          -        -       -         -            3         
u2.un1_lux_1_d1_49                              ORCALUT4     B        In      0.000     4.628 r      -         
u2.un1_lux_1_d1_49                              ORCALUT4     Z        Out     1.017     5.645 r      -         
un1_lux_1_d1_49                                 Net          -        -       -         -            1         
u2.un1_lux_1_s0_m1_0_cry_9_0                    CCU2D        C1       In      0.000     5.645 r      -         
u2.un1_lux_1_s0_m1_0_cry_9_0                    CCU2D        COUT     Out     1.544     7.189 r      -         
un1_lux_1_s0_m1_0_cry_10                        Net          -        -       -         -            1         
u2.un1_lux_1_s0_m1_0_cry_11_0                   CCU2D        CIN      In      0.000     7.189 r      -         
u2.un1_lux_1_s0_m1_0_cry_11_0                   CCU2D        COUT     Out     0.143     7.332 r      -         
un1_lux_1_s0_m1_0_cry_12                        Net          -        -       -         -            1         
u2.un1_lux_1_s0_m1_0_cry_13_0                   CCU2D        CIN      In      0.000     7.332 r      -         
u2.un1_lux_1_s0_m1_0_cry_13_0                   CCU2D        COUT     Out     0.143     7.475 r      -         
un1_lux_1_s0_m1_0_cry_14                        Net          -        -       -         -            1         
u2.un1_lux_1_s0_m1_0_cry_15_0                   CCU2D        CIN      In      0.000     7.475 r      -         
u2.un1_lux_1_s0_m1_0_cry_15_0                   CCU2D        COUT     Out     0.143     7.618 r      -         
un1_lux_1_s0_m1_0_cry_16                        Net          -        -       -         -            1         
u2.un1_lux_1_s0_m1_0_cry_17_0                   CCU2D        CIN      In      0.000     7.618 r      -         
u2.un1_lux_1_s0_m1_0_cry_17_0                   CCU2D        COUT     Out     0.143     7.761 r      -         
un1_lux_1_s0_m1_0_cry_18                        Net          -        -       -         -            1         
u2.un1_lux_1_s0_m1_0_cry_19_0                   CCU2D        CIN      In      0.000     7.761 r      -         
u2.un1_lux_1_s0_m1_0_cry_19_0                   CCU2D        COUT     Out     0.143     7.903 r      -         
un1_lux_1_s0_m1_0_cry_20                        Net          -        -       -         -            1         
u2.un1_lux_1_s0_m1_0_cry_21_0                   CCU2D        CIN      In      0.000     7.903 r      -         
u2.un1_lux_1_s0_m1_0_cry_21_0                   CCU2D        COUT     Out     0.143     8.046 r      -         
un1_lux_1_s0_m1_0_cry_22                        Net          -        -       -         -            1         
u2.un1_lux_1_s0_m1_0_cry_23_0                   CCU2D        CIN      In      0.000     8.046 r      -         
u2.un1_lux_1_s0_m1_0_cry_23_0                   CCU2D        COUT     Out     0.143     8.189 r      -         
un1_lux_1_s0_m1_0_cry_24                        Net          -        -       -         -            1         
u2.un1_lux_1_s0_m1_0_cry_25_0                   CCU2D        CIN      In      0.000     8.189 r      -         
u2.un1_lux_1_s0_m1_0_cry_25_0                   CCU2D        S0       Out     1.549     9.738 r      -         
un1_lux_1_s0_m1_0_cry_25_0_S0                   Net          -        -       -         -            1         
u2.un1_lux_1_s0_m1[27]                          ORCALUT4     A        In      0.000     9.738 r      -         
u2.un1_lux_1_s0_m1[27]                          ORCALUT4     Z        Out     1.017     10.755 r     -         
un1_lux_1_s0_m1[27]                             Net          -        -       -         -            1         
u2.un1_lux_1_s0_d[27]                           ORCALUT4     C        In      0.000     10.755 r     -         
u2.un1_lux_1_s0_d[27]                           ORCALUT4     Z        Out     1.193     11.948 r     -         
un1_lux_1_s0_d[27]                              Net          -        -       -         -            4         
u2.u1.CO2_0_0_mb_mb_1_0                         ORCALUT4     B        In      0.000     11.948 r     -         
u2.u1.CO2_0_0_mb_mb_1_0                         ORCALUT4     Z        Out     1.017     12.964 f     -         
shift_m1_e_1_1_0                                Net          -        -       -         -            1         
u2.u1.CO2_0_0_mb_mb                             ORCALUT4     A        In      0.000     12.964 f     -         
u2.u1.CO2_0_0_mb_mb                             ORCALUT4     Z        Out     1.089     14.053 r     -         
CO2_0_0                                         Net          -        -       -         -            2         
u2.u1.CO2_2_0                                   ORCALUT4     A        In      0.000     14.053 r     -         
u2.u1.CO2_2_0                                   ORCALUT4     Z        Out     1.089     15.142 r     -         
CO2_2_0                                         Net          -        -       -         -            2         
u2.u1.shift_reg_54_i_o3[37]                     ORCALUT4     B        In      0.000     15.142 r     -         
u2.u1.shift_reg_54_i_o3[37]                     ORCALUT4     Z        Out     1.225     16.367 r     -         
CO0_118                                         Net          -        -       -         -            5         
u2.u1.shift_reg_41[34]                          ORCALUT4     C        In      0.000     16.367 r     -         
u2.u1.shift_reg_41[34]                          ORCALUT4     Z        Out     1.277     17.644 r     -         
shift_reg_41[34]                                Net          -        -       -         -            10        
u2.u1.shift_reg_41_i_i_a2_RNIKQ44[32]           ORCALUT4     C        In      0.000     17.644 r     -         
u2.u1.shift_reg_41_i_i_a2_RNIKQ44[32]           ORCALUT4     Z        Out     1.017     18.660 r     -         
shift_reg_41_i_i_a2_RNIKQ44[32]                 Net          -        -       -         -            1         
u2.u1.shift_reg_41_i_i_a2_RNI7T8O[32]           ORCALUT4     D        In      0.000     18.660 r     -         
u2.u1.shift_reg_41_i_i_a2_RNI7T8O[32]           ORCALUT4     Z        Out     1.277     19.937 f     -         
CO2_108                                         Net          -        -       -         -            10        
u2.u1.shift_reg_51_RNIOB4OA[34]                 ORCALUT4     B        In      0.000     19.937 f     -         
u2.u1.shift_reg_51_RNIOB4OA[34]                 ORCALUT4     Z        Out     1.225     21.162 r     -         
CO1_112_fc                                      Net          -        -       -         -            5         
u2.u1.shift_reg_51_RNIE8KV51[34]                ORCALUT4     B        In      0.000     21.162 r     -         
u2.u1.shift_reg_51_RNIE8KV51[34]                ORCALUT4     Z        Out     1.089     22.251 r     -         
shift_reg_51_RNIE8KV51[34]                      Net          -        -       -         -            2         
u2.u1.shift_reg_61_RNI73H881[33]                ORCALUT4     A        In      0.000     22.251 r     -         
u2.u1.shift_reg_61_RNI73H881[33]                ORCALUT4     Z        Out     1.233     23.484 f     -         
CO1_108                                         Net          -        -       -         -            6         
u2.u1.shift_reg_87_N_2L1_1                      ORCALUT4     B        In      0.000     23.484 f     -         
u2.u1.shift_reg_87_N_2L1_1                      ORCALUT4     Z        Out     1.017     24.500 r     -         
shift_reg_87_N_2L1_1                            Net          -        -       -         -            1         
u2.u1.shift_reg_87[38]                          ORCALUT4     C        In      0.000     24.500 r     -         
u2.u1.shift_reg_87[38]                          ORCALUT4     Z        Out     1.193     25.693 r     -         
shift_reg_87[38]                                Net          -        -       -         -            4         
u2.u1.shift_reg_100[38]                         ORCALUT4     C        In      0.000     25.693 r     -         
u2.u1.shift_reg_100[38]                         ORCALUT4     Z        Out     1.193     26.886 r     -         
shift_reg_100[38]                               Net          -        -       -         -            4         
u2.u1.shift_reg_113_0_a2_0_a2[37]               ORCALUT4     C        In      0.000     26.886 r     -         
u2.u1.shift_reg_113_0_a2_0_a2[37]               ORCALUT4     Z        Out     1.233     28.119 r     -         
N_694                                           Net          -        -       -         -            6         
u2.u1.shift_reg_113_RNIEE992[38]                ORCALUT4     B        In      0.000     28.119 r     -         
u2.u1.shift_reg_113_RNIEE992[38]                ORCALUT4     Z        Out     1.017     29.136 r     -         
shift_reg_113_RNIEE992[38]                      Net          -        -       -         -            1         
u2.u1.shift_reg_113_RNINRTK3[39]                ORCALUT4     A        In      0.000     29.136 r     -         
u2.u1.shift_reg_113_RNINRTK3[39]                ORCALUT4     Z        Out     1.153     30.288 r     -         
CO1_90                                          Net          -        -       -         -            3         
u2.u1.shift_reg_113_0_a2_0_a2_RNIKPG78[37]      ORCALUT4     C        In      0.000     30.288 r     -         
u2.u1.shift_reg_113_0_a2_0_a2_RNIKPG78[37]      ORCALUT4     Z        Out     1.265     31.553 r     -         
CO2_85                                          Net          -        -       -         -            8         
u2.u1.shift_reg_145_N_2L1_0_RNIPU5A9            ORCALUT4     A        In      0.000     31.553 r     -         
u2.u1.shift_reg_145_N_2L1_0_RNIPU5A9            ORCALUT4     Z        Out     1.017     32.570 r     -         
shift_reg_145_N_2L1_0_RNIPU5A9                  Net          -        -       -         -            1         
u2.u1.shift_reg_145_i_i_a2_0_RNIDFJ8J[37]       ORCALUT4     B        In      0.000     32.570 r     -         
u2.u1.shift_reg_145_i_i_a2_0_RNIDFJ8J[37]       ORCALUT4     Z        Out     1.225     33.795 r     -         
CO2_80                                          Net          -        -       -         -            5         
u2.u1.shift_reg_161[38]                         ORCALUT4     B        In      0.000     33.795 r     -         
u2.u1.shift_reg_161[38]                         ORCALUT4     Z        Out     1.233     35.028 r     -         
shift_reg_161[38]                               Net          -        -       -         -            6         
u2.u1.shift_reg_161_RNI4KREM[38]                ORCALUT4     B        In      0.000     35.028 r     -         
u2.u1.shift_reg_161_RNI4KREM[38]                ORCALUT4     Z        Out     1.249     36.276 r     -         
CO0_74                                          Net          -        -       -         -            7         
u2.u1.shift_reg_161_0_a2_0_a2_RNICBNDN[37]      ORCALUT4     B        In      0.000     36.276 r     -         
u2.u1.shift_reg_161_0_a2_0_a2_RNICBNDN[37]      ORCALUT4     Z        Out     1.017     37.293 r     -         
CO1_67_1                                        Net          -        -       -         -            1         
u2.u1.shift_reg_199_i_i_a2_0_RNIC00HF1[37]      ORCALUT4     B        In      0.000     37.293 r     -         
u2.u1.shift_reg_199_i_i_a2_0_RNIC00HF1[37]      ORCALUT4     Z        Out     1.233     38.526 r     -         
CO1_67                                          Net          -        -       -         -            6         
u2.u1.shift_reg_180_0_a2_0_a2_RNIQ1HB72[37]     ORCALUT4     D        In      0.000     38.526 r     -         
u2.u1.shift_reg_180_0_a2_0_a2_RNIQ1HB72[37]     ORCALUT4     Z        Out     1.281     39.807 r     -         
CO2_63                                          Net          -        -       -         -            11        
u2.u1.shift_reg_180_RNINETUU2[38]               ORCALUT4     B        In      0.000     39.807 r     -         
u2.u1.shift_reg_180_RNINETUU2[38]               ORCALUT4     Z        Out     1.281     41.088 r     -         
CO0_62                                          Net          -        -       -         -            11        
u2.u1.shift_reg_240_i_i_a2_0[37]                ORCALUT4     B        In      0.000     41.088 r     -         
u2.u1.shift_reg_240_i_i_a2_0[37]                ORCALUT4     Z        Out     1.153     42.240 r     -         
shift_reg_240_i_i_a2_0[37]                      Net          -        -       -         -            3         
u2.u1.shift_reg_240_i_i_a2_0_RNI4FR695[37]      ORCALUT4     C        In      0.000     42.240 r     -         
u2.u1.shift_reg_240_i_i_a2_0_RNI4FR695[37]      ORCALUT4     Z        Out     1.193     43.433 r     -         
CO1_53                                          Net          -        -       -         -            4         
u2.u1.shift_reg_218_RNILMTP0O_0[38]             ORCALUT4     A        In      0.000     43.433 r     -         
u2.u1.shift_reg_218_RNILMTP0O_0[38]             ORCALUT4     Z        Out     1.273     44.706 r     -         
CO0_48                                          Net          -        -       -         -            9         
u2.u1.shift_reg_262[38]                         ORCALUT4     A        In      0.000     44.706 r     -         
u2.u1.shift_reg_262[38]                         ORCALUT4     Z        Out     1.265     45.971 r     -         
shift_reg_262[38]                               Net          -        -       -         -            8         
u2.u1.shift_reg_262_RNI4H628H[38]               ORCALUT4     C        In      0.000     45.971 r     -         
u2.u1.shift_reg_262_RNI4H628H[38]               ORCALUT4     Z        Out     1.153     47.124 r     -         
CO2_42                                          Net          -        -       -         -            3         
u2.u1.shift_reg_287_i_0_RNIHGFSIE1_0[41]        ORCALUT4     C        In      0.000     47.124 r     -         
u2.u1.shift_reg_287_i_0_RNIHGFSIE1_0[41]        ORCALUT4     Z        Out     1.017     48.140 r     -         
shift_reg_287_i_0_RNIHGFSIE1_0[41]              Net          -        -       -         -            1         
u2.u1.shift_reg_265_i_i_a2_RNIMA80LU2[41]       ORCALUT4     D        In      0.000     48.140 r     -         
u2.u1.shift_reg_265_i_i_a2_RNIMA80LU2[41]       ORCALUT4     Z        Out     1.017     49.157 f     -         
shift_reg_265_i_i_a2_RNIMA80LU2[41]             Net          -        -       -         -            1         
u2.u1.shift_reg_265_RNIV34TQE1[42]              ORCALUT4     C        In      0.000     49.157 f     -         
u2.u1.shift_reg_265_RNIV34TQE1[42]              ORCALUT4     Z        Out     1.305     50.462 r     -         
CO0_35                                          Net          -        -       -         -            15        
u2.u1.shift_reg_312[42]                         ORCALUT4     B        In      0.000     50.462 r     -         
u2.u1.shift_reg_312[42]                         ORCALUT4     Z        Out     1.249     51.711 r     -         
shift_reg_312[42]                               Net          -        -       -         -            7         
u2.u1.shift_reg_312_RNITFN4GL3[43]              ORCALUT4     C        In      0.000     51.711 r     -         
u2.u1.shift_reg_312_RNITFN4GL3[43]              ORCALUT4     Z        Out     1.273     52.984 r     -         
un1_shift_reg_axb0_0                            Net          -        -       -         -            9         
u2.u1._l27\.un1_shift_reg_c3_0_am               ORCALUT4     B        In      0.000     52.984 r     -         
u2.u1._l27\.un1_shift_reg_c3_0_am               ORCALUT4     Z        Out     1.017     54.000 f     -         
un1_shift_reg_c3_0_am                           Net          -        -       -         -            1         
u2.u1._l27\.un1_shift_reg_c3_0                  PFUMX        BLUT     In      0.000     54.000 f     -         
u2.u1._l27\.un1_shift_reg_c3_0                  PFUMX        Z        Out     0.470     54.471 f     -         
un1_shift_reg_0                                 Net          -        -       -         -            9         
u2.u1._l27\.shift_reg_365_axbxc2_0_bm           ORCALUT4     D        In      0.000     54.471 f     -         
u2.u1._l27\.shift_reg_365_axbxc2_0_bm           ORCALUT4     Z        Out     1.017     55.487 r     -         
shift_reg_365_axbxc2_0_bm                       Net          -        -       -         -            1         
u2.u1._l27\.shift_reg_365_axbxc2_0              PFUMX        ALUT     In      0.000     55.487 r     -         
u2.u1._l27\.shift_reg_365_axbxc2_0              PFUMX        Z        Out     0.422     55.910 r     -         
shift_reg_365[47]                               Net          -        -       -         -            5         
u2.u1._l28\.shift_reg_393_axbxc1_N_2L1          ORCALUT4     A        In      0.000     55.910 r     -         
u2.u1._l28\.shift_reg_393_axbxc1_N_2L1          ORCALUT4     Z        Out     1.017     56.926 f     -         
shift_reg_393_axbxc1_N_2L1                      Net          -        -       -         -            1         
u2.u1._l28\.shift_reg_393_axbxc1                ORCALUT4     C        In      0.000     56.926 f     -         
u2.u1._l28\.shift_reg_393_axbxc1                ORCALUT4     Z        Out     1.273     58.199 r     -         
shift_reg_393[46]                               Net          -        -       -         -            9         
u2.u1._l29\.shift_reg_421_axbxc1_1              ORCALUT4     A        In      0.000     58.199 r     -         
u2.u1._l29\.shift_reg_421_axbxc1_1              ORCALUT4     Z        Out     1.017     59.216 f     -         
_m2_7_1                                         Net          -        -       -         -            1         
u2.u1._l29\.shift_reg_421_axbxc1                ORCALUT4     D        In      0.000     59.216 f     -         
u2.u1._l29\.shift_reg_421_axbxc1                ORCALUT4     Z        Out     1.265     60.481 r     -         
shift_reg_421[46]                               Net          -        -       -         -            8         
u2.u1._l30\.un1_shift_reg_3_ac0_5               ORCALUT4     B        In      0.000     60.481 r     -         
u2.u1._l30\.un1_shift_reg_3_ac0_5               ORCALUT4     Z        Out     1.089     61.570 f     -         
un1_shift_reg_3                                 Net          -        -       -         -            2         
u2.u1._l30\.shift_reg_449_axbxc2                ORCALUT4     D        In      0.000     61.570 f     -         
u2.u1._l30\.shift_reg_449_axbxc2                ORCALUT4     Z        Out     1.017     62.586 r     -         
shift_reg_449[47]                               Net          -        -       -         -            1         
u2.u1._l30\.shift_reg_449_axbxc2_RNI5P8VIA      ORCALUT4     C        In      0.000     62.586 r     -         
u2.u1._l30\.shift_reg_449_axbxc2_RNI5P8VIA      ORCALUT4     Z        Out     1.317     63.903 r     -         
shift_reg_477[47]                               Net          -        -       -         -            18        
u4.data_6_14_8_.m8                              ORCALUT4     A        In      0.000     63.903 r     -         
u4.data_6_14_8_.m8                              ORCALUT4     Z        Out     1.017     64.920 r     -         
N_9_0                                           Net          -        -       -         -            1         
u4.data_12_1_d[9]                               ORCALUT4     D        In      0.000     64.920 r     -         
u4.data_12_1_d[9]                               ORCALUT4     Z        Out     1.017     65.937 f     -         
data_12_1_d[9]                                  Net          -        -       -         -            1         
u4.data_12_3_d_d_0[9]                           PFUMX        BLUT     In      0.000     65.937 f     -         
u4.data_12_3_d_d_0[9]                           PFUMX        Z        Out     0.214     66.151 f     -         
data_12_3_d_d_0[9]                              Net          -        -       -         -            1         
u4.data_12_3_d[9]                               ORCALUT4     A        In      0.000     66.151 f     -         
u4.data_12_3_d[9]                               ORCALUT4     Z        Out     1.017     67.168 f     -         
data_12_3_d[9]                                  Net          -        -       -         -            1         
u4.data_12_7_am[9]                              ORCALUT4     B        In      0.000     67.168 f     -         
u4.data_12_7_am[9]                              ORCALUT4     Z        Out     1.017     68.185 f     -         
data_12_7_am[9]                                 Net          -        -       -         -            1         
u4.data_12_7[9]                                 PFUMX        BLUT     In      0.000     68.185 f     -         
u4.data_12_7[9]                                 PFUMX        Z        Out     0.214     68.399 f     -         
data_12[9]                                      Net          -        -       -         -            1         
u4.data[9]                                      FD1P3AX      D        In      0.000     68.399 f     -         
===============================================================================================================


Path information for path number 3: 
      Requested Period:                      5.000
    - Setup time:                            -0.462
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         5.462

    - Propagation time:                      68.399
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -62.936

    Number of logic level(s):                67
    Starting point:                          u1.ch1_dat[7] / Q
    Ending point:                            u4.data[9] / D
    The start point is clocked by            rpr0521rs_driver|clk_400khz_derived_clock [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK
    The end   point is clocked by            segment_scan|clk_40khz_derived_clock [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK

Instance / Net                                               Pin      Pin               Arrival      No. of    
Name                                            Type         Name     Dir     Delay     Time         Fan Out(s)
---------------------------------------------------------------------------------------------------------------
u1.ch1_dat[7]                                   FD1P3AX      Q        Out     1.256     1.256 r      -         
ch1_dat[7]                                      Net          -        -       -         -            14        
u2.un1_ch1_dat_1_cry_6_0                        CCU2D        A1       In      0.000     1.256 r      -         
u2.un1_ch1_dat_1_cry_6_0                        CCU2D        COUT     Out     1.544     2.800 r      -         
un1_ch1_dat_1_cry_7                             Net          -        -       -         -            1         
u2.un1_ch1_dat_1_cry_8_0                        CCU2D        CIN      In      0.000     2.800 r      -         
u2.un1_ch1_dat_1_cry_8_0                        CCU2D        S0       Out     1.685     4.485 r      -         
un1_ch1_dat_1[8]                                Net          -        -       -         -            3         
u2.un1_lux_1_d1_39                              ORCALUT4     B        In      0.000     4.485 r      -         
u2.un1_lux_1_d1_39                              ORCALUT4     Z        Out     1.017     5.502 r      -         
un1_lux_1_d1_39                                 Net          -        -       -         -            1         
u2.un1_lux_1_s0_m1_0_cry_7_0                    CCU2D        C1       In      0.000     5.502 r      -         
u2.un1_lux_1_s0_m1_0_cry_7_0                    CCU2D        COUT     Out     1.544     7.047 r      -         
un1_lux_1_s0_m1_0_cry_8                         Net          -        -       -         -            1         
u2.un1_lux_1_s0_m1_0_cry_9_0                    CCU2D        CIN      In      0.000     7.047 r      -         
u2.un1_lux_1_s0_m1_0_cry_9_0                    CCU2D        COUT     Out     0.143     7.189 r      -         
un1_lux_1_s0_m1_0_cry_10                        Net          -        -       -         -            1         
u2.un1_lux_1_s0_m1_0_cry_11_0                   CCU2D        CIN      In      0.000     7.189 r      -         
u2.un1_lux_1_s0_m1_0_cry_11_0                   CCU2D        COUT     Out     0.143     7.332 r      -         
un1_lux_1_s0_m1_0_cry_12                        Net          -        -       -         -            1         
u2.un1_lux_1_s0_m1_0_cry_13_0                   CCU2D        CIN      In      0.000     7.332 r      -         
u2.un1_lux_1_s0_m1_0_cry_13_0                   CCU2D        COUT     Out     0.143     7.475 r      -         
un1_lux_1_s0_m1_0_cry_14                        Net          -        -       -         -            1         
u2.un1_lux_1_s0_m1_0_cry_15_0                   CCU2D        CIN      In      0.000     7.475 r      -         
u2.un1_lux_1_s0_m1_0_cry_15_0                   CCU2D        COUT     Out     0.143     7.618 r      -         
un1_lux_1_s0_m1_0_cry_16                        Net          -        -       -         -            1         
u2.un1_lux_1_s0_m1_0_cry_17_0                   CCU2D        CIN      In      0.000     7.618 r      -         
u2.un1_lux_1_s0_m1_0_cry_17_0                   CCU2D        COUT     Out     0.143     7.761 r      -         
un1_lux_1_s0_m1_0_cry_18                        Net          -        -       -         -            1         
u2.un1_lux_1_s0_m1_0_cry_19_0                   CCU2D        CIN      In      0.000     7.761 r      -         
u2.un1_lux_1_s0_m1_0_cry_19_0                   CCU2D        COUT     Out     0.143     7.903 r      -         
un1_lux_1_s0_m1_0_cry_20                        Net          -        -       -         -            1         
u2.un1_lux_1_s0_m1_0_cry_21_0                   CCU2D        CIN      In      0.000     7.903 r      -         
u2.un1_lux_1_s0_m1_0_cry_21_0                   CCU2D        COUT     Out     0.143     8.046 r      -         
un1_lux_1_s0_m1_0_cry_22                        Net          -        -       -         -            1         
u2.un1_lux_1_s0_m1_0_cry_23_0                   CCU2D        CIN      In      0.000     8.046 r      -         
u2.un1_lux_1_s0_m1_0_cry_23_0                   CCU2D        COUT     Out     0.143     8.189 r      -         
un1_lux_1_s0_m1_0_cry_24                        Net          -        -       -         -            1         
u2.un1_lux_1_s0_m1_0_cry_25_0                   CCU2D        CIN      In      0.000     8.189 r      -         
u2.un1_lux_1_s0_m1_0_cry_25_0                   CCU2D        S0       Out     1.549     9.738 r      -         
un1_lux_1_s0_m1_0_cry_25_0_S0                   Net          -        -       -         -            1         
u2.un1_lux_1_s0_m1[27]                          ORCALUT4     A        In      0.000     9.738 r      -         
u2.un1_lux_1_s0_m1[27]                          ORCALUT4     Z        Out     1.017     10.755 r     -         
un1_lux_1_s0_m1[27]                             Net          -        -       -         -            1         
u2.un1_lux_1_s0_d[27]                           ORCALUT4     C        In      0.000     10.755 r     -         
u2.un1_lux_1_s0_d[27]                           ORCALUT4     Z        Out     1.193     11.948 r     -         
un1_lux_1_s0_d[27]                              Net          -        -       -         -            4         
u2.u1.CO2_0_0_mb_mb_1_0                         ORCALUT4     B        In      0.000     11.948 r     -         
u2.u1.CO2_0_0_mb_mb_1_0                         ORCALUT4     Z        Out     1.017     12.964 f     -         
shift_m1_e_1_1_0                                Net          -        -       -         -            1         
u2.u1.CO2_0_0_mb_mb                             ORCALUT4     A        In      0.000     12.964 f     -         
u2.u1.CO2_0_0_mb_mb                             ORCALUT4     Z        Out     1.089     14.053 r     -         
CO2_0_0                                         Net          -        -       -         -            2         
u2.u1.CO2_2_0                                   ORCALUT4     A        In      0.000     14.053 r     -         
u2.u1.CO2_2_0                                   ORCALUT4     Z        Out     1.089     15.142 r     -         
CO2_2_0                                         Net          -        -       -         -            2         
u2.u1.shift_reg_54_i_o3[37]                     ORCALUT4     B        In      0.000     15.142 r     -         
u2.u1.shift_reg_54_i_o3[37]                     ORCALUT4     Z        Out     1.225     16.367 r     -         
CO0_118                                         Net          -        -       -         -            5         
u2.u1.shift_reg_41[34]                          ORCALUT4     C        In      0.000     16.367 r     -         
u2.u1.shift_reg_41[34]                          ORCALUT4     Z        Out     1.277     17.644 r     -         
shift_reg_41[34]                                Net          -        -       -         -            10        
u2.u1.shift_reg_41_i_i_a2_RNIKQ44[32]           ORCALUT4     C        In      0.000     17.644 r     -         
u2.u1.shift_reg_41_i_i_a2_RNIKQ44[32]           ORCALUT4     Z        Out     1.017     18.660 r     -         
shift_reg_41_i_i_a2_RNIKQ44[32]                 Net          -        -       -         -            1         
u2.u1.shift_reg_41_i_i_a2_RNI7T8O[32]           ORCALUT4     D        In      0.000     18.660 r     -         
u2.u1.shift_reg_41_i_i_a2_RNI7T8O[32]           ORCALUT4     Z        Out     1.277     19.937 f     -         
CO2_108                                         Net          -        -       -         -            10        
u2.u1.shift_reg_51_RNIOB4OA[34]                 ORCALUT4     B        In      0.000     19.937 f     -         
u2.u1.shift_reg_51_RNIOB4OA[34]                 ORCALUT4     Z        Out     1.225     21.162 r     -         
CO1_112_fc                                      Net          -        -       -         -            5         
u2.u1.shift_reg_51_RNIE8KV51[34]                ORCALUT4     B        In      0.000     21.162 r     -         
u2.u1.shift_reg_51_RNIE8KV51[34]                ORCALUT4     Z        Out     1.089     22.251 r     -         
shift_reg_51_RNIE8KV51[34]                      Net          -        -       -         -            2         
u2.u1.shift_reg_61_RNI73H881[33]                ORCALUT4     A        In      0.000     22.251 r     -         
u2.u1.shift_reg_61_RNI73H881[33]                ORCALUT4     Z        Out     1.233     23.484 f     -         
CO1_108                                         Net          -        -       -         -            6         
u2.u1.shift_reg_87_N_2L1_1                      ORCALUT4     B        In      0.000     23.484 f     -         
u2.u1.shift_reg_87_N_2L1_1                      ORCALUT4     Z        Out     1.017     24.500 r     -         
shift_reg_87_N_2L1_1                            Net          -        -       -         -            1         
u2.u1.shift_reg_87[38]                          ORCALUT4     C        In      0.000     24.500 r     -         
u2.u1.shift_reg_87[38]                          ORCALUT4     Z        Out     1.193     25.693 r     -         
shift_reg_87[38]                                Net          -        -       -         -            4         
u2.u1.shift_reg_100_0_a2_0_a2[37]               ORCALUT4     C        In      0.000     25.693 r     -         
u2.u1.shift_reg_100_0_a2_0_a2[37]               ORCALUT4     Z        Out     1.193     26.886 r     -         
ANB1_100                                        Net          -        -       -         -            4         
u2.u1.shift_reg_113_0_a2_0_a2[37]               ORCALUT4     A        In      0.000     26.886 r     -         
u2.u1.shift_reg_113_0_a2_0_a2[37]               ORCALUT4     Z        Out     1.233     28.119 r     -         
N_694                                           Net          -        -       -         -            6         
u2.u1.shift_reg_113_RNIEE992[38]                ORCALUT4     B        In      0.000     28.119 r     -         
u2.u1.shift_reg_113_RNIEE992[38]                ORCALUT4     Z        Out     1.017     29.136 r     -         
shift_reg_113_RNIEE992[38]                      Net          -        -       -         -            1         
u2.u1.shift_reg_113_RNINRTK3[39]                ORCALUT4     A        In      0.000     29.136 r     -         
u2.u1.shift_reg_113_RNINRTK3[39]                ORCALUT4     Z        Out     1.153     30.288 r     -         
CO1_90                                          Net          -        -       -         -            3         
u2.u1.shift_reg_113_0_a2_0_a2_RNIKPG78[37]      ORCALUT4     C        In      0.000     30.288 r     -         
u2.u1.shift_reg_113_0_a2_0_a2_RNIKPG78[37]      ORCALUT4     Z        Out     1.265     31.553 r     -         
CO2_85                                          Net          -        -       -         -            8         
u2.u1.shift_reg_145_N_2L1_0_RNIPU5A9            ORCALUT4     A        In      0.000     31.553 r     -         
u2.u1.shift_reg_145_N_2L1_0_RNIPU5A9            ORCALUT4     Z        Out     1.017     32.570 r     -         
shift_reg_145_N_2L1_0_RNIPU5A9                  Net          -        -       -         -            1         
u2.u1.shift_reg_145_i_i_a2_0_RNIDFJ8J[37]       ORCALUT4     B        In      0.000     32.570 r     -         
u2.u1.shift_reg_145_i_i_a2_0_RNIDFJ8J[37]       ORCALUT4     Z        Out     1.225     33.795 r     -         
CO2_80                                          Net          -        -       -         -            5         
u2.u1.shift_reg_161[38]                         ORCALUT4     B        In      0.000     33.795 r     -         
u2.u1.shift_reg_161[38]                         ORCALUT4     Z        Out     1.233     35.028 r     -         
shift_reg_161[38]                               Net          -        -       -         -            6         
u2.u1.shift_reg_161_RNI4KREM[38]                ORCALUT4     B        In      0.000     35.028 r     -         
u2.u1.shift_reg_161_RNI4KREM[38]                ORCALUT4     Z        Out     1.249     36.276 r     -         
CO0_74                                          Net          -        -       -         -            7         
u2.u1.shift_reg_161_0_a2_0_a2_RNICBNDN[37]      ORCALUT4     B        In      0.000     36.276 r     -         
u2.u1.shift_reg_161_0_a2_0_a2_RNICBNDN[37]      ORCALUT4     Z        Out     1.017     37.293 r     -         
CO1_67_1                                        Net          -        -       -         -            1         
u2.u1.shift_reg_199_i_i_a2_0_RNIC00HF1[37]      ORCALUT4     B        In      0.000     37.293 r     -         
u2.u1.shift_reg_199_i_i_a2_0_RNIC00HF1[37]      ORCALUT4     Z        Out     1.233     38.526 r     -         
CO1_67                                          Net          -        -       -         -            6         
u2.u1.shift_reg_180_0_a2_0_a2_RNIQ1HB72[37]     ORCALUT4     D        In      0.000     38.526 r     -         
u2.u1.shift_reg_180_0_a2_0_a2_RNIQ1HB72[37]     ORCALUT4     Z        Out     1.281     39.807 r     -         
CO2_63                                          Net          -        -       -         -            11        
u2.u1.shift_reg_180_RNINETUU2[38]               ORCALUT4     B        In      0.000     39.807 r     -         
u2.u1.shift_reg_180_RNINETUU2[38]               ORCALUT4     Z        Out     1.281     41.088 r     -         
CO0_62                                          Net          -        -       -         -            11        
u2.u1.shift_reg_240_i_i_a2_0[37]                ORCALUT4     B        In      0.000     41.088 r     -         
u2.u1.shift_reg_240_i_i_a2_0[37]                ORCALUT4     Z        Out     1.153     42.240 r     -         
shift_reg_240_i_i_a2_0[37]                      Net          -        -       -         -            3         
u2.u1.shift_reg_240_i_i_a2_0_RNI4FR695[37]      ORCALUT4     C        In      0.000     42.240 r     -         
u2.u1.shift_reg_240_i_i_a2_0_RNI4FR695[37]      ORCALUT4     Z        Out     1.193     43.433 r     -         
CO1_53                                          Net          -        -       -         -            4         
u2.u1.shift_reg_218_RNILMTP0O_0[38]             ORCALUT4     A        In      0.000     43.433 r     -         
u2.u1.shift_reg_218_RNILMTP0O_0[38]             ORCALUT4     Z        Out     1.273     44.706 r     -         
CO0_48                                          Net          -        -       -         -            9         
u2.u1.shift_reg_262[38]                         ORCALUT4     A        In      0.000     44.706 r     -         
u2.u1.shift_reg_262[38]                         ORCALUT4     Z        Out     1.265     45.971 r     -         
shift_reg_262[38]                               Net          -        -       -         -            8         
u2.u1.shift_reg_262_RNI4H628H[38]               ORCALUT4     C        In      0.000     45.971 r     -         
u2.u1.shift_reg_262_RNI4H628H[38]               ORCALUT4     Z        Out     1.153     47.124 r     -         
CO2_42                                          Net          -        -       -         -            3         
u2.u1.shift_reg_287_i_0_RNIHGFSIE1_0[41]        ORCALUT4     C        In      0.000     47.124 r     -         
u2.u1.shift_reg_287_i_0_RNIHGFSIE1_0[41]        ORCALUT4     Z        Out     1.017     48.140 r     -         
shift_reg_287_i_0_RNIHGFSIE1_0[41]              Net          -        -       -         -            1         
u2.u1.shift_reg_265_i_i_a2_RNIMA80LU2[41]       ORCALUT4     D        In      0.000     48.140 r     -         
u2.u1.shift_reg_265_i_i_a2_RNIMA80LU2[41]       ORCALUT4     Z        Out     1.017     49.157 f     -         
shift_reg_265_i_i_a2_RNIMA80LU2[41]             Net          -        -       -         -            1         
u2.u1.shift_reg_265_RNIV34TQE1[42]              ORCALUT4     C        In      0.000     49.157 f     -         
u2.u1.shift_reg_265_RNIV34TQE1[42]              ORCALUT4     Z        Out     1.305     50.462 r     -         
CO0_35                                          Net          -        -       -         -            15        
u2.u1.shift_reg_312[42]                         ORCALUT4     B        In      0.000     50.462 r     -         
u2.u1.shift_reg_312[42]                         ORCALUT4     Z        Out     1.249     51.711 r     -         
shift_reg_312[42]                               Net          -        -       -         -            7         
u2.u1.shift_reg_312_RNITFN4GL3[43]              ORCALUT4     C        In      0.000     51.711 r     -         
u2.u1.shift_reg_312_RNITFN4GL3[43]              ORCALUT4     Z        Out     1.273     52.984 r     -         
un1_shift_reg_axb0_0                            Net          -        -       -         -            9         
u2.u1._l27\.un1_shift_reg_c3_0_am               ORCALUT4     B        In      0.000     52.984 r     -         
u2.u1._l27\.un1_shift_reg_c3_0_am               ORCALUT4     Z        Out     1.017     54.000 f     -         
un1_shift_reg_c3_0_am                           Net          -        -       -         -            1         
u2.u1._l27\.un1_shift_reg_c3_0                  PFUMX        BLUT     In      0.000     54.000 f     -         
u2.u1._l27\.un1_shift_reg_c3_0                  PFUMX        Z        Out     0.470     54.471 f     -         
un1_shift_reg_0                                 Net          -        -       -         -            9         
u2.u1._l27\.shift_reg_365_axbxc2_0_bm           ORCALUT4     D        In      0.000     54.471 f     -         
u2.u1._l27\.shift_reg_365_axbxc2_0_bm           ORCALUT4     Z        Out     1.017     55.487 r     -         
shift_reg_365_axbxc2_0_bm                       Net          -        -       -         -            1         
u2.u1._l27\.shift_reg_365_axbxc2_0              PFUMX        ALUT     In      0.000     55.487 r     -         
u2.u1._l27\.shift_reg_365_axbxc2_0              PFUMX        Z        Out     0.422     55.910 r     -         
shift_reg_365[47]                               Net          -        -       -         -            5         
u2.u1._l28\.shift_reg_393_axbxc1_N_2L1          ORCALUT4     A        In      0.000     55.910 r     -         
u2.u1._l28\.shift_reg_393_axbxc1_N_2L1          ORCALUT4     Z        Out     1.017     56.926 f     -         
shift_reg_393_axbxc1_N_2L1                      Net          -        -       -         -            1         
u2.u1._l28\.shift_reg_393_axbxc1                ORCALUT4     C        In      0.000     56.926 f     -         
u2.u1._l28\.shift_reg_393_axbxc1                ORCALUT4     Z        Out     1.273     58.199 r     -         
shift_reg_393[46]                               Net          -        -       -         -            9         
u2.u1._l29\.shift_reg_421_axbxc1_1              ORCALUT4     A        In      0.000     58.199 r     -         
u2.u1._l29\.shift_reg_421_axbxc1_1              ORCALUT4     Z        Out     1.017     59.216 f     -         
_m2_7_1                                         Net          -        -       -         -            1         
u2.u1._l29\.shift_reg_421_axbxc1                ORCALUT4     D        In      0.000     59.216 f     -         
u2.u1._l29\.shift_reg_421_axbxc1                ORCALUT4     Z        Out     1.265     60.481 r     -         
shift_reg_421[46]                               Net          -        -       -         -            8         
u2.u1._l30\.un1_shift_reg_3_ac0_5               ORCALUT4     B        In      0.000     60.481 r     -         
u2.u1._l30\.un1_shift_reg_3_ac0_5               ORCALUT4     Z        Out     1.089     61.570 f     -         
un1_shift_reg_3                                 Net          -        -       -         -            2         
u2.u1._l30\.shift_reg_449_axbxc2                ORCALUT4     D        In      0.000     61.570 f     -         
u2.u1._l30\.shift_reg_449_axbxc2                ORCALUT4     Z        Out     1.017     62.586 r     -         
shift_reg_449[47]                               Net          -        -       -         -            1         
u2.u1._l30\.shift_reg_449_axbxc2_RNI5P8VIA      ORCALUT4     C        In      0.000     62.586 r     -         
u2.u1._l30\.shift_reg_449_axbxc2_RNI5P8VIA      ORCALUT4     Z        Out     1.317     63.903 r     -         
shift_reg_477[47]                               Net          -        -       -         -            18        
u4.data_6_14_8_.m8                              ORCALUT4     A        In      0.000     63.903 r     -         
u4.data_6_14_8_.m8                              ORCALUT4     Z        Out     1.017     64.920 r     -         
N_9_0                                           Net          -        -       -         -            1         
u4.data_12_1_d[9]                               ORCALUT4     D        In      0.000     64.920 r     -         
u4.data_12_1_d[9]                               ORCALUT4     Z        Out     1.017     65.937 f     -         
data_12_1_d[9]                                  Net          -        -       -         -            1         
u4.data_12_3_d_d_0[9]                           PFUMX        BLUT     In      0.000     65.937 f     -         
u4.data_12_3_d_d_0[9]                           PFUMX        Z        Out     0.214     66.151 f     -         
data_12_3_d_d_0[9]                              Net          -        -       -         -            1         
u4.data_12_3_d[9]                               ORCALUT4     A        In      0.000     66.151 f     -         
u4.data_12_3_d[9]                               ORCALUT4     Z        Out     1.017     67.168 f     -         
data_12_3_d[9]                                  Net          -        -       -         -            1         
u4.data_12_7_am[9]                              ORCALUT4     B        In      0.000     67.168 f     -         
u4.data_12_7_am[9]                              ORCALUT4     Z        Out     1.017     68.185 f     -         
data_12_7_am[9]                                 Net          -        -       -         -            1         
u4.data_12_7[9]                                 PFUMX        BLUT     In      0.000     68.185 f     -         
u4.data_12_7[9]                                 PFUMX        Z        Out     0.214     68.399 f     -         
data_12[9]                                      Net          -        -       -         -            1         
u4.data[9]                                      FD1P3AX      D        In      0.000     68.399 f     -         
===============================================================================================================




====================================
<a name=clockReport39></a>Detailed Report for Clock: rpr0521rs_driver|dat_valid_derived_clock</a>
====================================



<a name=startingSlack40></a>Starting Points with Worst Slack</a>
********************************

                    Starting                                                                          Arrival          
Instance            Reference                                    Type        Pin     Net              Time        Slack
                    Clock                                                                                              
-----------------------------------------------------------------------------------------------------------------------
u2.prox_dat0[0]     rpr0521rs_driver|dat_valid_derived_clock     FD1S3AX     Q       prox_dat0[0]     1.044       2.365
u2.prox_dat1[0]     rpr0521rs_driver|dat_valid_derived_clock     FD1S3AX     Q       prox_dat1[0]     0.972       2.437
u2.prox_dat0[1]     rpr0521rs_driver|dat_valid_derived_clock     FD1S3AX     Q       prox_dat0[1]     1.044       2.507
u2.prox_dat0[2]     rpr0521rs_driver|dat_valid_derived_clock     FD1S3AX     Q       prox_dat0[2]     1.044       2.507
u2.prox_dat1[1]     rpr0521rs_driver|dat_valid_derived_clock     FD1S3AX     Q       prox_dat1[1]     0.972       2.579
u2.prox_dat1[2]     rpr0521rs_driver|dat_valid_derived_clock     FD1S3AX     Q       prox_dat1[2]     0.972       2.579
u2.prox_dat0[3]     rpr0521rs_driver|dat_valid_derived_clock     FD1S3AX     Q       prox_dat0[3]     1.044       2.650
u2.prox_dat0[4]     rpr0521rs_driver|dat_valid_derived_clock     FD1S3AX     Q       prox_dat0[4]     1.044       2.650
u2.prox_dat1[3]     rpr0521rs_driver|dat_valid_derived_clock     FD1S3AX     Q       prox_dat1[3]     0.972       2.722
u2.prox_dat1[4]     rpr0521rs_driver|dat_valid_derived_clock     FD1S3AX     Q       prox_dat1[4]     0.972       2.722
=======================================================================================================================


<a name=endingSlack41></a>Ending Points with Worst Slack</a>
******************************

                     Starting                                                                                  Required          
Instance             Reference                                    Type        Pin     Net                      Time         Slack
                     Clock                                                                                                       
---------------------------------------------------------------------------------------------------------------------------------
u2.prox_dat2[9]      rpr0521rs_driver|dat_valid_derived_clock     FD1P3AX     SP      un1_prox_dat0_2lto15     9.528        2.365
u2.prox_dat2[10]     rpr0521rs_driver|dat_valid_derived_clock     FD1P3AX     SP      un1_prox_dat0_2lto15     9.528        2.365
u2.prox_dat2[11]     rpr0521rs_driver|dat_valid_derived_clock     FD1P3AX     SP      un1_prox_dat0_2lto15     9.528        2.365
u2.prox_dat1[9]      rpr0521rs_driver|dat_valid_derived_clock     FD1S3AX     D       prox_dat0[9]             9.894        8.787
u2.prox_dat1[10]     rpr0521rs_driver|dat_valid_derived_clock     FD1S3AX     D       prox_dat0[10]            9.894        8.787
u2.prox_dat1[11]     rpr0521rs_driver|dat_valid_derived_clock     FD1S3AX     D       prox_dat0[11]            9.894        8.787
u2.prox_dat2[9]      rpr0521rs_driver|dat_valid_derived_clock     FD1P3AX     D       prox_dat0[9]             9.894        8.787
u2.prox_dat2[10]     rpr0521rs_driver|dat_valid_derived_clock     FD1P3AX     D       prox_dat0[10]            9.894        8.787
u2.prox_dat2[11]     rpr0521rs_driver|dat_valid_derived_clock     FD1P3AX     D       prox_dat0[11]            9.894        8.787
u2.prox_dat1[0]      rpr0521rs_driver|dat_valid_derived_clock     FD1S3AX     D       prox_dat0[0]             9.894        8.851
=================================================================================================================================



<a name=worstPaths42></a>Worst Path Information</a>
<a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\impl1\prox_detect_impl1.srr:srsfD:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\impl1\prox_detect_impl1.srs:fp:195153:198321:@XP_NAMES_GATE">View Worst Path in Analyst</a>
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            0.472
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.528

    - Propagation time:                      7.164
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 2.365

    Number of logic level(s):                10
    Starting point:                          u2.prox_dat0[0] / Q
    Ending point:                            u2.prox_dat2[9] / SP
    The start point is clocked by            rpr0521rs_driver|dat_valid_derived_clock [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK
    The end   point is clocked by            rpr0521rs_driver|dat_valid_derived_clock [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK
    -Timing constraint applied as multi cycle path with factor 2 (from c:rpr0521rs_driver|dat_valid_derived_clock to c:rpr0521rs_driver|dat_valid_derived_clock)

Instance / Net                               Pin      Pin               Arrival     No. of    
Name                            Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------
u2.prox_dat0[0]                 FD1S3AX      Q        Out     1.044     1.044 r     -         
prox_dat0[0]                    Net          -        -       -         -           2         
u2.un1_prox_dat0_1_cry_0_0      CCU2D        B1       In      0.000     1.044 r     -         
u2.un1_prox_dat0_1_cry_0_0      CCU2D        COUT     Out     1.544     2.588 r     -         
un1_prox_dat0_1_cry_0           Net          -        -       -         -           1         
u2.un1_prox_dat0_1_cry_1_0      CCU2D        CIN      In      0.000     2.588 r     -         
u2.un1_prox_dat0_1_cry_1_0      CCU2D        COUT     Out     0.143     2.731 r     -         
un1_prox_dat0_1_cry_2           Net          -        -       -         -           1         
u2.un1_prox_dat0_1_cry_3_0      CCU2D        CIN      In      0.000     2.731 r     -         
u2.un1_prox_dat0_1_cry_3_0      CCU2D        COUT     Out     0.143     2.874 r     -         
un1_prox_dat0_1_cry_4           Net          -        -       -         -           1         
u2.un1_prox_dat0_1_cry_5_0      CCU2D        CIN      In      0.000     2.874 r     -         
u2.un1_prox_dat0_1_cry_5_0      CCU2D        COUT     Out     0.143     3.017 r     -         
un1_prox_dat0_1_cry_6           Net          -        -       -         -           1         
u2.un1_prox_dat0_1_cry_7_0      CCU2D        CIN      In      0.000     3.017 r     -         
u2.un1_prox_dat0_1_cry_7_0      CCU2D        COUT     Out     0.143     3.159 r     -         
un1_prox_dat0_1_cry_8           Net          -        -       -         -           1         
u2.un1_prox_dat0_1_cry_9_0      CCU2D        CIN      In      0.000     3.159 r     -         
u2.un1_prox_dat0_1_cry_9_0      CCU2D        COUT     Out     0.143     3.302 r     -         
un1_prox_dat0_1_cry_10          Net          -        -       -         -           1         
u2.un1_prox_dat0_1_cry_11_0     CCU2D        CIN      In      0.000     3.302 r     -         
u2.un1_prox_dat0_1_cry_11_0     CCU2D        COUT     Out     0.143     3.445 r     -         
un1_prox_dat0_1_cry_12          Net          -        -       -         -           1         
u2.un1_prox_dat0_1_cry_13_0     CCU2D        CIN      In      0.000     3.445 r     -         
u2.un1_prox_dat0_1_cry_13_0     CCU2D        S1       Out     1.549     4.994 r     -         
un1_prox_dat0_1[14]             Net          -        -       -         -           1         
u2.un1_prox_dat0_2lto15_1       ORCALUT4     B        In      0.000     4.994 r     -         
u2.un1_prox_dat0_2lto15_1       ORCALUT4     Z        Out     1.017     6.011 f     -         
un1_prox_dat0_2lto15_1          Net          -        -       -         -           1         
u2.un1_prox_dat0_2lto15         ORCALUT4     D        In      0.000     6.011 f     -         
u2.un1_prox_dat0_2lto15         ORCALUT4     Z        Out     1.153     7.164 f     -         
un1_prox_dat0_2lto15            Net          -        -       -         -           3         
u2.prox_dat2[9]                 FD1P3AX      SP       In      0.000     7.164 f     -         
==============================================================================================


Path information for path number 2: 
      Requested Period:                      10.000
    - Setup time:                            0.472
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.528

    - Propagation time:                      7.164
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 2.365

    Number of logic level(s):                10
    Starting point:                          u2.prox_dat0[0] / Q
    Ending point:                            u2.prox_dat2[9] / SP
    The start point is clocked by            rpr0521rs_driver|dat_valid_derived_clock [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK
    The end   point is clocked by            rpr0521rs_driver|dat_valid_derived_clock [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK
    -Timing constraint applied as multi cycle path with factor 2 (from c:rpr0521rs_driver|dat_valid_derived_clock to c:rpr0521rs_driver|dat_valid_derived_clock)

Instance / Net                               Pin      Pin               Arrival     No. of    
Name                            Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------
u2.prox_dat0[0]                 FD1S3AX      Q        Out     1.044     1.044 r     -         
prox_dat0[0]                    Net          -        -       -         -           2         
u2.un1_prox_dat0_1_cry_0_0      CCU2D        B1       In      0.000     1.044 r     -         
u2.un1_prox_dat0_1_cry_0_0      CCU2D        COUT     Out     1.544     2.588 r     -         
un1_prox_dat0_1_cry_0           Net          -        -       -         -           1         
u2.un1_prox_dat0_1_cry_1_0      CCU2D        CIN      In      0.000     2.588 r     -         
u2.un1_prox_dat0_1_cry_1_0      CCU2D        COUT     Out     0.143     2.731 r     -         
un1_prox_dat0_1_cry_2           Net          -        -       -         -           1         
u2.un1_prox_dat0_1_cry_3_0      CCU2D        CIN      In      0.000     2.731 r     -         
u2.un1_prox_dat0_1_cry_3_0      CCU2D        COUT     Out     0.143     2.874 r     -         
un1_prox_dat0_1_cry_4           Net          -        -       -         -           1         
u2.un1_prox_dat0_1_cry_5_0      CCU2D        CIN      In      0.000     2.874 r     -         
u2.un1_prox_dat0_1_cry_5_0      CCU2D        COUT     Out     0.143     3.017 r     -         
un1_prox_dat0_1_cry_6           Net          -        -       -         -           1         
u2.un1_prox_dat0_1_cry_7_0      CCU2D        CIN      In      0.000     3.017 r     -         
u2.un1_prox_dat0_1_cry_7_0      CCU2D        COUT     Out     0.143     3.159 r     -         
un1_prox_dat0_1_cry_8           Net          -        -       -         -           1         
u2.un1_prox_dat0_1_cry_9_0      CCU2D        CIN      In      0.000     3.159 r     -         
u2.un1_prox_dat0_1_cry_9_0      CCU2D        COUT     Out     0.143     3.302 r     -         
un1_prox_dat0_1_cry_10          Net          -        -       -         -           1         
u2.un1_prox_dat0_1_cry_11_0     CCU2D        CIN      In      0.000     3.302 r     -         
u2.un1_prox_dat0_1_cry_11_0     CCU2D        COUT     Out     0.143     3.445 r     -         
un1_prox_dat0_1_cry_12          Net          -        -       -         -           1         
u2.un1_prox_dat0_1_cry_13_0     CCU2D        CIN      In      0.000     3.445 r     -         
u2.un1_prox_dat0_1_cry_13_0     CCU2D        S0       Out     1.549     4.994 r     -         
un1_prox_dat0_1[13]             Net          -        -       -         -           1         
u2.un1_prox_dat0_2lto15_1       ORCALUT4     A        In      0.000     4.994 r     -         
u2.un1_prox_dat0_2lto15_1       ORCALUT4     Z        Out     1.017     6.011 f     -         
un1_prox_dat0_2lto15_1          Net          -        -       -         -           1         
u2.un1_prox_dat0_2lto15         ORCALUT4     D        In      0.000     6.011 f     -         
u2.un1_prox_dat0_2lto15         ORCALUT4     Z        Out     1.153     7.164 f     -         
un1_prox_dat0_2lto15            Net          -        -       -         -           3         
u2.prox_dat2[9]                 FD1P3AX      SP       In      0.000     7.164 f     -         
==============================================================================================


Path information for path number 3: 
      Requested Period:                      10.000
    - Setup time:                            0.472
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.528

    - Propagation time:                      7.164
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 2.365

    Number of logic level(s):                10
    Starting point:                          u2.prox_dat0[0] / Q
    Ending point:                            u2.prox_dat2[11] / SP
    The start point is clocked by            rpr0521rs_driver|dat_valid_derived_clock [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK
    The end   point is clocked by            rpr0521rs_driver|dat_valid_derived_clock [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK
    -Timing constraint applied as multi cycle path with factor 2 (from c:rpr0521rs_driver|dat_valid_derived_clock to c:rpr0521rs_driver|dat_valid_derived_clock)

Instance / Net                               Pin      Pin               Arrival     No. of    
Name                            Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------
u2.prox_dat0[0]                 FD1S3AX      Q        Out     1.044     1.044 r     -         
prox_dat0[0]                    Net          -        -       -         -           2         
u2.un1_prox_dat0_1_cry_0_0      CCU2D        B1       In      0.000     1.044 r     -         
u2.un1_prox_dat0_1_cry_0_0      CCU2D        COUT     Out     1.544     2.588 r     -         
un1_prox_dat0_1_cry_0           Net          -        -       -         -           1         
u2.un1_prox_dat0_1_cry_1_0      CCU2D        CIN      In      0.000     2.588 r     -         
u2.un1_prox_dat0_1_cry_1_0      CCU2D        COUT     Out     0.143     2.731 r     -         
un1_prox_dat0_1_cry_2           Net          -        -       -         -           1         
u2.un1_prox_dat0_1_cry_3_0      CCU2D        CIN      In      0.000     2.731 r     -         
u2.un1_prox_dat0_1_cry_3_0      CCU2D        COUT     Out     0.143     2.874 r     -         
un1_prox_dat0_1_cry_4           Net          -        -       -         -           1         
u2.un1_prox_dat0_1_cry_5_0      CCU2D        CIN      In      0.000     2.874 r     -         
u2.un1_prox_dat0_1_cry_5_0      CCU2D        COUT     Out     0.143     3.017 r     -         
un1_prox_dat0_1_cry_6           Net          -        -       -         -           1         
u2.un1_prox_dat0_1_cry_7_0      CCU2D        CIN      In      0.000     3.017 r     -         
u2.un1_prox_dat0_1_cry_7_0      CCU2D        COUT     Out     0.143     3.159 r     -         
un1_prox_dat0_1_cry_8           Net          -        -       -         -           1         
u2.un1_prox_dat0_1_cry_9_0      CCU2D        CIN      In      0.000     3.159 r     -         
u2.un1_prox_dat0_1_cry_9_0      CCU2D        COUT     Out     0.143     3.302 r     -         
un1_prox_dat0_1_cry_10          Net          -        -       -         -           1         
u2.un1_prox_dat0_1_cry_11_0     CCU2D        CIN      In      0.000     3.302 r     -         
u2.un1_prox_dat0_1_cry_11_0     CCU2D        COUT     Out     0.143     3.445 r     -         
un1_prox_dat0_1_cry_12          Net          -        -       -         -           1         
u2.un1_prox_dat0_1_cry_13_0     CCU2D        CIN      In      0.000     3.445 r     -         
u2.un1_prox_dat0_1_cry_13_0     CCU2D        S1       Out     1.549     4.994 r     -         
un1_prox_dat0_1[14]             Net          -        -       -         -           1         
u2.un1_prox_dat0_2lto15_1       ORCALUT4     B        In      0.000     4.994 r     -         
u2.un1_prox_dat0_2lto15_1       ORCALUT4     Z        Out     1.017     6.011 f     -         
un1_prox_dat0_2lto15_1          Net          -        -       -         -           1         
u2.un1_prox_dat0_2lto15         ORCALUT4     D        In      0.000     6.011 f     -         
u2.un1_prox_dat0_2lto15         ORCALUT4     Z        Out     1.153     7.164 f     -         
un1_prox_dat0_2lto15            Net          -        -       -         -           3         
u2.prox_dat2[11]                FD1P3AX      SP       In      0.000     7.164 f     -         
==============================================================================================




====================================
<a name=clockReport43></a>Detailed Report for Clock: segment_scan|clk_40khz_derived_clock</a>
====================================



<a name=startingSlack44></a>Starting Points with Worst Slack</a>
********************************

                    Starting                                                                      Arrival          
Instance            Reference                                Type        Pin     Net              Time        Slack
                    Clock                                                                                          
-------------------------------------------------------------------------------------------------------------------
u4.cnt_write[1]     segment_scan|clk_40khz_derived_clock     FD1P3AX     Q       cnt_write[1]     1.232       2.810
u4.cnt_write[2]     segment_scan|clk_40khz_derived_clock     FD1P3AX     Q       cnt_write[2]     1.188       2.854
u4.cnt_write[4]     segment_scan|clk_40khz_derived_clock     FD1P3AX     Q       cnt_write[4]     1.148       2.894
u4.cnt_write[3]     segment_scan|clk_40khz_derived_clock     FD1P3AX     Q       cnt_write[3]     1.108       2.934
u4.cnt_main[1]      segment_scan|clk_40khz_derived_clock     FD1S3AX     Q       cnt_main[1]      1.326       3.847
u4.state[1]         segment_scan|clk_40khz_derived_clock     FD1S3AX     Q       state[1]         1.252       4.015
u4.cnt_write[0]     segment_scan|clk_40khz_derived_clock     FD1P3AX     Q       cnt_write[0]     1.204       4.063
u4.cnt_write[5]     segment_scan|clk_40khz_derived_clock     FD1P3AX     Q       cnt_write[5]     1.204       4.063
u4.cnt_main[2]      segment_scan|clk_40khz_derived_clock     FD1S3AX     Q       cnt_main[2]      1.345       4.344
u4.state[0]         segment_scan|clk_40khz_derived_clock     FD1S3AX     Q       state[0]         1.236       6.980
===================================================================================================================


<a name=endingSlack45></a>Ending Points with Worst Slack</a>
******************************

                    Starting                                                                        Required          
Instance            Reference                                Type        Pin     Net                Time         Slack
                    Clock                                                                                             
----------------------------------------------------------------------------------------------------------------------
u4.cnt_write[5]     segment_scan|clk_40khz_derived_clock     FD1P3AX     D       cnt_write_s[5]     9.894        2.810
u4.cnt_write[3]     segment_scan|clk_40khz_derived_clock     FD1P3AX     D       cnt_write_s[3]     9.894        2.953
u4.cnt_write[4]     segment_scan|clk_40khz_derived_clock     FD1P3AX     D       cnt_write_s[4]     9.894        2.953
u4.cnt_write[1]     segment_scan|clk_40khz_derived_clock     FD1P3AX     D       cnt_write_s[1]     9.894        3.095
u4.cnt_write[2]     segment_scan|clk_40khz_derived_clock     FD1P3AX     D       cnt_write_s[2]     9.894        3.095
u4.data[10]         segment_scan|clk_40khz_derived_clock     FD1P3AX     D       data_12[10]        10.089       3.847
u4.data[8]          segment_scan|clk_40khz_derived_clock     FD1P3AX     D       data_12[8]         10.089       4.344
u4.cnt_write[0]     segment_scan|clk_40khz_derived_clock     FD1P3AX     SP      N_119_i            9.528        4.822
u4.cnt_write[1]     segment_scan|clk_40khz_derived_clock     FD1P3AX     SP      N_119_i            9.528        4.822
u4.cnt_write[2]     segment_scan|clk_40khz_derived_clock     FD1P3AX     SP      N_119_i            9.528        4.822
======================================================================================================================



<a name=worstPaths46></a>Worst Path Information</a>
<a href="D:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\impl1\prox_detect_impl1.srr:srsfD:\BaiduNetdiskDownload\V4.0\lab8_prox_detect\impl1\prox_detect_impl1.srs:fp:212895:215058:@XP_NAMES_GATE">View Worst Path in Analyst</a>
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            0.106
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.894

    - Propagation time:                      7.085
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 2.810

    Number of logic level(s):                6
    Starting point:                          u4.cnt_write[1] / Q
    Ending point:                            u4.cnt_write[5] / D
    The start point is clocked by            segment_scan|clk_40khz_derived_clock [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK
    The end   point is clocked by            segment_scan|clk_40khz_derived_clock [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK
    -Timing constraint applied as multi cycle path with factor 2 (from c:segment_scan|clk_40khz_derived_clock to c:segment_scan|clk_40khz_derived_clock)

Instance / Net                                      Pin      Pin               Arrival     No. of    
Name                                   Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------
u4.cnt_write[1]                        FD1P3AX      Q        Out     1.232     1.232 r     -         
cnt_write[1]                           Net          -        -       -         -           10        
u4.state_ns_0_a2_0_a2_1[0]             ORCALUT4     A        In      0.000     1.232 r     -         
u4.state_ns_0_a2_0_a2_1[0]             ORCALUT4     Z        Out     1.225     2.457 f     -         
N_169                                  Net          -        -       -         -           5         
u4.state_ns_0_a2_0_a2_1_RNIKPGV[0]     ORCALUT4     D        In      0.000     2.457 f     -         
u4.state_ns_0_a2_0_a2_1_RNIKPGV[0]     ORCALUT4     Z        Out     1.249     3.705 f     -         
cnt_write                              Net          -        -       -         -           7         
u4.cnt_write_cry_0[0]                  CCU2D        A1       In      0.000     3.705 f     -         
u4.cnt_write_cry_0[0]                  CCU2D        COUT     Out     1.544     5.250 r     -         
cnt_write_cry[0]                       Net          -        -       -         -           1         
u4.cnt_write_cry_0[1]                  CCU2D        CIN      In      0.000     5.250 r     -         
u4.cnt_write_cry_0[1]                  CCU2D        COUT     Out     0.143     5.393 r     -         
cnt_write_cry[2]                       Net          -        -       -         -           1         
u4.cnt_write_cry_0[3]                  CCU2D        CIN      In      0.000     5.393 r     -         
u4.cnt_write_cry_0[3]                  CCU2D        COUT     Out     0.143     5.535 r     -         
cnt_write_cry[4]                       Net          -        -       -         -           1         
u4.cnt_write_s_0[5]                    CCU2D        CIN      In      0.000     5.535 r     -         
u4.cnt_write_s_0[5]                    CCU2D        S0       Out     1.549     7.085 r     -         
cnt_write_s[5]                         Net          -        -       -         -           1         
u4.cnt_write[5]                        FD1P3AX      D        In      0.000     7.085 r     -         
=====================================================================================================


Path information for path number 2: 
      Requested Period:                      10.000
    - Setup time:                            0.106
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.894

    - Propagation time:                      7.085
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 2.810

    Number of logic level(s):                6
    Starting point:                          u4.cnt_write[1] / Q
    Ending point:                            u4.cnt_write[5] / D
    The start point is clocked by            segment_scan|clk_40khz_derived_clock [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK
    The end   point is clocked by            segment_scan|clk_40khz_derived_clock [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK
    -Timing constraint applied as multi cycle path with factor 2 (from c:segment_scan|clk_40khz_derived_clock to c:segment_scan|clk_40khz_derived_clock)

Instance / Net                                      Pin      Pin               Arrival     No. of    
Name                                   Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------
u4.cnt_write[1]                        FD1P3AX      Q        Out     1.232     1.232 r     -         
cnt_write[1]                           Net          -        -       -         -           10        
u4.state_ns_0_a2_0_a2_1[0]             ORCALUT4     A        In      0.000     1.232 r     -         
u4.state_ns_0_a2_0_a2_1[0]             ORCALUT4     Z        Out     1.225     2.457 f     -         
N_169                                  Net          -        -       -         -           5         
u4.state_ns_0_a2_0_a2_1_RNIKPGV[0]     ORCALUT4     D        In      0.000     2.457 f     -         
u4.state_ns_0_a2_0_a2_1_RNIKPGV[0]     ORCALUT4     Z        Out     1.249     3.705 f     -         
cnt_write                              Net          -        -       -         -           7         
u4.cnt_write_cry_0[0]                  CCU2D        B0       In      0.000     3.705 f     -         
u4.cnt_write_cry_0[0]                  CCU2D        COUT     Out     1.544     5.250 r     -         
cnt_write_cry[0]                       Net          -        -       -         -           1         
u4.cnt_write_cry_0[1]                  CCU2D        CIN      In      0.000     5.250 r     -         
u4.cnt_write_cry_0[1]                  CCU2D        COUT     Out     0.143     5.393 r     -         
cnt_write_cry[2]                       Net          -        -       -         -           1         
u4.cnt_write_cry_0[3]                  CCU2D        CIN      In      0.000     5.393 r     -         
u4.cnt_write_cry_0[3]                  CCU2D        COUT     Out     0.143     5.535 r     -         
cnt_write_cry[4]                       Net          -        -       -         -           1         
u4.cnt_write_s_0[5]                    CCU2D        CIN      In      0.000     5.535 r     -         
u4.cnt_write_s_0[5]                    CCU2D        S0       Out     1.549     7.085 r     -         
cnt_write_s[5]                         Net          -        -       -         -           1         
u4.cnt_write[5]                        FD1P3AX      D        In      0.000     7.085 r     -         
=====================================================================================================


Path information for path number 3: 
      Requested Period:                      10.000
    - Setup time:                            0.106
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.894

    - Propagation time:                      7.040
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 2.854

    Number of logic level(s):                6
    Starting point:                          u4.cnt_write[2] / Q
    Ending point:                            u4.cnt_write[5] / D
    The start point is clocked by            segment_scan|clk_40khz_derived_clock [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK
    The end   point is clocked by            segment_scan|clk_40khz_derived_clock [rising] (rise=0.000 fall=2.500 period=5.000) on pin CK
    -Timing constraint applied as multi cycle path with factor 2 (from c:segment_scan|clk_40khz_derived_clock to c:segment_scan|clk_40khz_derived_clock)

Instance / Net                                      Pin      Pin               Arrival     No. of    
Name                                   Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------
u4.cnt_write[2]                        FD1P3AX      Q        Out     1.188     1.188 r     -         
cnt_write[2]                           Net          -        -       -         -           6         
u4.state_ns_0_a2_0_a2_1[0]             ORCALUT4     B        In      0.000     1.188 r     -         
u4.state_ns_0_a2_0_a2_1[0]             ORCALUT4     Z        Out     1.225     2.413 f     -         
N_169                                  Net          -        -       -         -           5         
u4.state_ns_0_a2_0_a2_1_RNIKPGV[0]     ORCALUT4     D        In      0.000     2.413 f     -         
u4.state_ns_0_a2_0_a2_1_RNIKPGV[0]     ORCALUT4     Z        Out     1.249     3.661 f     -         
cnt_write                              Net          -        -       -         -           7         
u4.cnt_write_cry_0[0]                  CCU2D        A1       In      0.000     3.661 f     -         
u4.cnt_write_cry_0[0]                  CCU2D        COUT     Out     1.544     5.206 r     -         
cnt_write_cry[0]                       Net          -        -       -         -           1         
u4.cnt_write_cry_0[1]                  CCU2D        CIN      In      0.000     5.206 r     -         
u4.cnt_write_cry_0[1]                  CCU2D        COUT     Out     0.143     5.349 r     -         
cnt_write_cry[2]                       Net          -        -       -         -           1         
u4.cnt_write_cry_0[3]                  CCU2D        CIN      In      0.000     5.349 r     -         
u4.cnt_write_cry_0[3]                  CCU2D        COUT     Out     0.143     5.492 r     -         
cnt_write_cry[4]                       Net          -        -       -         -           1         
u4.cnt_write_s_0[5]                    CCU2D        CIN      In      0.000     5.492 r     -         
u4.cnt_write_s_0[5]                    CCU2D        S0       Out     1.549     7.040 r     -         
cnt_write_s[5]                         Net          -        -       -         -           1         
u4.cnt_write[5]                        FD1P3AX      D        In      0.000     7.040 r     -         
=====================================================================================================



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied

Finished final timing analysis (Real Time elapsed 0h:02m:04s; CPU Time elapsed 0h:02m:03s; Memory used current: 295MB peak: 527MB)


Finished timing report (Real Time elapsed 0h:02m:04s; CPU Time elapsed 0h:02m:03s; Memory used current: 295MB peak: 527MB)

---------------------------------------
<a name=resourceUsage47></a>Resource Usage Report</a>
Part: lcmxo2_4000hc-5

Register bits: 570 of 4320 (13%)
PIC Latch:       0
I/O cells:       19


Details:
BB:             1
CCU2D:          526
FD1P3AX:        460
FD1P3AY:        3
FD1S3AX:        101
FD1S3AY:        1
GSR:            1
IB:             2
IFS1P3DX:       1
INV:            17
L6MUX21:        23
OB:             16
OFS1P3BX:       1
OFS1P3DX:       3
ORCALUT4:       1523
PFUMX:          79
PUR:            1
VHI:            5
VLO:            5
Mapper successful!

At Mapper Exit (Real Time elapsed 0h:02m:05s; CPU Time elapsed 0h:02m:03s; Memory used current: 89MB peak: 527MB)

Process took 0h:02m:05s realtime, 0h:02m:03s cputime
# Wed Mar  5 03:16:39 2025

###########################################################]

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